Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism in...
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Veröffentlicht in: | IEEE transactions on computers 2010-07, Vol.59 (7), p.905-921 |
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creator | Seong, Yoon Jae Nam, Eyee Hyun Yoon, Jin Hyuk Kim, Hongseok Choi, Jin-yong Lee, Sookwan Bae, Young Hyun Lee, Jaejin Cho, Yookun Min, Sang Lyul |
description | Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered. |
doi_str_mv | 10.1109/TC.2010.63 |
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fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TC_2010_63</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5432160</ieee_id><sourcerecordid>753726580</sourcerecordid><originalsourceid>FETCH-LOGICAL-c311t-4d3016ebeaee49f0d8aefcd00335a71854020849866e6d9659d20b41773af24e3</originalsourceid><addsrcrecordid>eNpd0M1Lw0AQBfBFFKzVi1cvAQ-CkDr7may3Gq0ttCi0nsM2O6Fpt03dTQ79702pePD0ePBjGB4htxQGlIJ-WmQDBl1R_Iz0qJRJrLVU56QHQNNYcwGX5CqENQAoBrpHJuOD9eY5GkYvri428czs92ijT-ONc-iikTNhFc1wW_tDNK9dZeN5YxqMXquwiYa-WFUNFk3r8ZpclMYFvPnNPvkavS2ycTz9eJ9kw2lccEqbWFgOVOESDaLQJdjUYFlYAM6lSWgqBTBIhU6VQmW1ktoyWAqaJNyUTCDvk4fT3b2vv1sMTb6tQoHOmR3WbcgTyROmZAqdvP8n13Xrd91zOQWWMBBM0049nlTh6xA8lvneV1vjDx3Kj6Pmiyw_jpor3uG7E64Q8Q9KwRlVwH8A0GVvUw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1027204291</pqid></control><display><type>article</type><title>Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture</title><source>IEEE Electronic Library (IEL)</source><creator>Seong, Yoon Jae ; Nam, Eyee Hyun ; Yoon, Jin Hyuk ; Kim, Hongseok ; Choi, Jin-yong ; Lee, Sookwan ; Bae, Young Hyun ; Lee, Jaejin ; Cho, Yookun ; Min, Sang Lyul</creator><creatorcontrib>Seong, Yoon Jae ; Nam, Eyee Hyun ; Yoon, Jin Hyuk ; Kim, Hongseok ; Choi, Jin-yong ; Lee, Sookwan ; Bae, Young Hyun ; Lee, Jaejin ; Cho, Yookun ; Min, Sang Lyul</creatorcontrib><description>Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.</description><identifier>ISSN: 0018-9340</identifier><identifier>EISSN: 1557-9956</identifier><identifier>DOI: 10.1109/TC.2010.63</identifier><identifier>CODEN: ITCOB4</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Architecture ; Bandwidth ; Blocking ; Chips (memory devices) ; Computer memory ; Controllers ; Disk drives ; Disks ; Flash memory ; Flash memory (computers) ; flash translation layer (FTL) ; Memory ; Memory architecture ; Nonvolatile memory ; Parallel processing ; Power consumption ; Random access memory ; Semiconductors ; solid-state disk (SSD) ; storage system</subject><ispartof>IEEE transactions on computers, 2010-07, Vol.59 (7), p.905-921</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jul 2010</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c311t-4d3016ebeaee49f0d8aefcd00335a71854020849866e6d9659d20b41773af24e3</citedby><cites>FETCH-LOGICAL-c311t-4d3016ebeaee49f0d8aefcd00335a71854020849866e6d9659d20b41773af24e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5432160$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27926,27927,54760</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5432160$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Seong, Yoon Jae</creatorcontrib><creatorcontrib>Nam, Eyee Hyun</creatorcontrib><creatorcontrib>Yoon, Jin Hyuk</creatorcontrib><creatorcontrib>Kim, Hongseok</creatorcontrib><creatorcontrib>Choi, Jin-yong</creatorcontrib><creatorcontrib>Lee, Sookwan</creatorcontrib><creatorcontrib>Bae, Young Hyun</creatorcontrib><creatorcontrib>Lee, Jaejin</creatorcontrib><creatorcontrib>Cho, Yookun</creatorcontrib><creatorcontrib>Min, Sang Lyul</creatorcontrib><title>Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture</title><title>IEEE transactions on computers</title><addtitle>TC</addtitle><description>Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.</description><subject>Architecture</subject><subject>Bandwidth</subject><subject>Blocking</subject><subject>Chips (memory devices)</subject><subject>Computer memory</subject><subject>Controllers</subject><subject>Disk drives</subject><subject>Disks</subject><subject>Flash memory</subject><subject>Flash memory (computers)</subject><subject>flash translation layer (FTL)</subject><subject>Memory</subject><subject>Memory architecture</subject><subject>Nonvolatile memory</subject><subject>Parallel processing</subject><subject>Power consumption</subject><subject>Random access memory</subject><subject>Semiconductors</subject><subject>solid-state disk (SSD)</subject><subject>storage system</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpd0M1Lw0AQBfBFFKzVi1cvAQ-CkDr7may3Gq0ttCi0nsM2O6Fpt03dTQ79702pePD0ePBjGB4htxQGlIJ-WmQDBl1R_Iz0qJRJrLVU56QHQNNYcwGX5CqENQAoBrpHJuOD9eY5GkYvri428czs92ijT-ONc-iikTNhFc1wW_tDNK9dZeN5YxqMXquwiYa-WFUNFk3r8ZpclMYFvPnNPvkavS2ycTz9eJ9kw2lccEqbWFgOVOESDaLQJdjUYFlYAM6lSWgqBTBIhU6VQmW1ktoyWAqaJNyUTCDvk4fT3b2vv1sMTb6tQoHOmR3WbcgTyROmZAqdvP8n13Xrd91zOQWWMBBM0049nlTh6xA8lvneV1vjDx3Kj6Pmiyw_jpor3uG7E64Q8Q9KwRlVwH8A0GVvUw</recordid><startdate>20100701</startdate><enddate>20100701</enddate><creator>Seong, Yoon Jae</creator><creator>Nam, Eyee Hyun</creator><creator>Yoon, Jin Hyuk</creator><creator>Kim, Hongseok</creator><creator>Choi, Jin-yong</creator><creator>Lee, Sookwan</creator><creator>Bae, Young Hyun</creator><creator>Lee, Jaejin</creator><creator>Cho, Yookun</creator><creator>Min, Sang Lyul</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20100701</creationdate><title>Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture</title><author>Seong, Yoon Jae ; Nam, Eyee Hyun ; Yoon, Jin Hyuk ; Kim, Hongseok ; Choi, Jin-yong ; Lee, Sookwan ; Bae, Young Hyun ; Lee, Jaejin ; Cho, Yookun ; Min, Sang Lyul</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c311t-4d3016ebeaee49f0d8aefcd00335a71854020849866e6d9659d20b41773af24e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Architecture</topic><topic>Bandwidth</topic><topic>Blocking</topic><topic>Chips (memory devices)</topic><topic>Computer memory</topic><topic>Controllers</topic><topic>Disk drives</topic><topic>Disks</topic><topic>Flash memory</topic><topic>Flash memory (computers)</topic><topic>flash translation layer (FTL)</topic><topic>Memory</topic><topic>Memory architecture</topic><topic>Nonvolatile memory</topic><topic>Parallel processing</topic><topic>Power consumption</topic><topic>Random access memory</topic><topic>Semiconductors</topic><topic>solid-state disk (SSD)</topic><topic>storage system</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Seong, Yoon Jae</creatorcontrib><creatorcontrib>Nam, Eyee Hyun</creatorcontrib><creatorcontrib>Yoon, Jin Hyuk</creatorcontrib><creatorcontrib>Kim, Hongseok</creatorcontrib><creatorcontrib>Choi, Jin-yong</creatorcontrib><creatorcontrib>Lee, Sookwan</creatorcontrib><creatorcontrib>Bae, Young Hyun</creatorcontrib><creatorcontrib>Lee, Jaejin</creatorcontrib><creatorcontrib>Cho, Yookun</creatorcontrib><creatorcontrib>Min, Sang Lyul</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Seong, Yoon Jae</au><au>Nam, Eyee Hyun</au><au>Yoon, Jin Hyuk</au><au>Kim, Hongseok</au><au>Choi, Jin-yong</au><au>Lee, Sookwan</au><au>Bae, Young Hyun</au><au>Lee, Jaejin</au><au>Cho, Yookun</au><au>Min, Sang Lyul</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>2010-07-01</date><risdate>2010</risdate><volume>59</volume><issue>7</issue><spage>905</spage><epage>921</epage><pages>905-921</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TC.2010.63</doi><tpages>17</tpages></addata></record> |
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subjects | Architecture Bandwidth Blocking Chips (memory devices) Computer memory Controllers Disk drives Disks Flash memory Flash memory (computers) flash translation layer (FTL) Memory Memory architecture Nonvolatile memory Parallel processing Power consumption Random access memory Semiconductors solid-state disk (SSD) storage system |
title | Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture |
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