Distributed Virtual Bit-Slice Synchronizer: A Scalable Hardware Barrier Mechanism for n-Dimensional Meshes

The work presents a distributed hardware-level barrier mechanism for n-dimensional mesh-connected MIMD computers, called Distributed Virtual Bit-Slice Synchronizer (DVBSS). The proposed mechanism is structured around an m-bit dedicated control network, whose topology is a directed mesh-embeddable gr...

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Veröffentlicht in:IEEE transactions on computers 2010-09, Vol.59 (9), p.1187-1199
1. Verfasser: Zotov, Igor Valerievich
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description The work presents a distributed hardware-level barrier mechanism for n-dimensional mesh-connected MIMD computers, called Distributed Virtual Bit-Slice Synchronizer (DVBSS). The proposed mechanism is structured around an m-bit dedicated control network, whose topology is a directed mesh-embeddable graph, with an additional m-bit-wide wraparound connection. By using a specific virtualization scheme making it possible to have p virtual m-bit barrier networks superposed on a physical one, the DVBSS model allows to synchronize more than m barrier groups. To minimize synchronization latency, the DVBSS scheme uses a distributed circulating wave clocking (DCW-clocking) technique to switch between virtual barrier networks in a pipeline fashion. The DVBSS scheme is shown to be general, configurable, and MPI-compatible. Unlike proposed distributed hardware barriers, and hardware tree-based schemes, the DVBSS mechanism accepts dynamically defined (possibly overlapping) barrier groups of arbitrary size and shape, allowing noncontiguous group member allocations.
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subjects Barrier synchronization
Barriers
Circulating
Computer simulation
Data mining
Decision support systems
dedicated barrier networks
Hardware
hardware barriers
Mathematical models
mesh-connected parallel computers
Networks
Switching theory
Synchronism
Synchronizers
title Distributed Virtual Bit-Slice Synchronizer: A Scalable Hardware Barrier Mechanism for n-Dimensional Meshes
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