The identification of a minimal feedback vertex set of a directed graph
This paper describes an algorithm for the identification of a minimal feedback vertex set of an arbitrary directed graph. Such a set of vertices has the property that removal of these vertices from the graph eliminates all directed loops. An efficient solution to this identification problem is a fam...
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Veröffentlicht in: | IEEE transactions on circuits and systems 1975-01, Vol.22 (1), p.9-15 |
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creator | Smith, G. Walford, R. |
description | This paper describes an algorithm for the identification of a minimal feedback vertex set of an arbitrary directed graph. Such a set of vertices has the property that removal of these vertices from the graph eliminates all directed loops. An efficient solution to this identification problem is a familiar unsolved problem of contemporary graph theory. Although pathological examples exist for which excessive computation v2 time may be required, the described algorithm appears to be quite v efficient for large graphs arising in practical applications. The algorithm seems to have great potential in the field of test generation for sequential logic circuits and certain types of simulation algorithms. No attempt is V3 made to impose restrictive conditions on the particular minimum feedback vertex set selected, although such restrictions may at times be desirable. The algorithm has been implemented on an IBM 360/67 and has been successfully applied to practical (logic circuit) problems having in excess of 2500 vertices. |
doi_str_mv | 10.1109/TCS.1975.1083961 |
format | Article |
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Such a set of vertices has the property that removal of these vertices from the graph eliminates all directed loops. An efficient solution to this identification problem is a familiar unsolved problem of contemporary graph theory. Although pathological examples exist for which excessive computation v2 time may be required, the described algorithm appears to be quite v efficient for large graphs arising in practical applications. The algorithm seems to have great potential in the field of test generation for sequential logic circuits and certain types of simulation algorithms. No attempt is V3 made to impose restrictive conditions on the particular minimum feedback vertex set selected, although such restrictions may at times be desirable. The algorithm has been implemented on an IBM 360/67 and has been successfully applied to practical (logic circuit) problems having in excess of 2500 vertices.</description><identifier>ISSN: 0098-4094</identifier><identifier>EISSN: 1558-1276</identifier><identifier>DOI: 10.1109/TCS.1975.1083961</identifier><identifier>CODEN: ICSYBT</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; Circuit testing ; Computational modeling ; Feedback ; Graph theory ; Logic circuits ; Logic testing ; Pathology ; Sequential analysis ; Sequential circuits</subject><ispartof>IEEE transactions on circuits and systems, 1975-01, Vol.22 (1), p.9-15</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c327t-ed01670c922d1e183e4a09b40b3852f6d13d77fffdff539bac00b71010b57fd93</citedby><cites>FETCH-LOGICAL-c327t-ed01670c922d1e183e4a09b40b3852f6d13d77fffdff539bac00b71010b57fd93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1083961$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27929,27930,54763</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1083961$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Smith, G.</creatorcontrib><creatorcontrib>Walford, R.</creatorcontrib><title>The identification of a minimal feedback vertex set of a directed graph</title><title>IEEE transactions on circuits and systems</title><addtitle>T-CAS</addtitle><description>This paper describes an algorithm for the identification of a minimal feedback vertex set of an arbitrary directed graph. Such a set of vertices has the property that removal of these vertices from the graph eliminates all directed loops. An efficient solution to this identification problem is a familiar unsolved problem of contemporary graph theory. Although pathological examples exist for which excessive computation v2 time may be required, the described algorithm appears to be quite v efficient for large graphs arising in practical applications. The algorithm seems to have great potential in the field of test generation for sequential logic circuits and certain types of simulation algorithms. No attempt is V3 made to impose restrictive conditions on the particular minimum feedback vertex set selected, although such restrictions may at times be desirable. The algorithm has been implemented on an IBM 360/67 and has been successfully applied to practical (logic circuit) problems having in excess of 2500 vertices.</description><subject>Circuit simulation</subject><subject>Circuit testing</subject><subject>Computational modeling</subject><subject>Feedback</subject><subject>Graph theory</subject><subject>Logic circuits</subject><subject>Logic testing</subject><subject>Pathology</subject><subject>Sequential analysis</subject><subject>Sequential circuits</subject><issn>0098-4094</issn><issn>1558-1276</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1975</creationdate><recordtype>article</recordtype><recordid>eNpNkE1LxDAQhoMoWFfvgpf8gdaZpm2SoxRdhQUP1nNJm4kb3W2XpIj-e7t0D57m8H4ND2O3CBki6PumfstQyzJDUEJXeMYSLEuVYi6rc5YAaJUWoItLdhXjJwAorVTC1s2WuLc0TN753kx-HPjouOF7P_i92XFHZDvTf_FvChP98EjTYrA-UD-R5R_BHLbX7MKZXaSb012x96fHpn5ON6_rl_phk_Yil1NKFrCS0Os8t0ioBBUGdFdAJ1SZu8qisFI656xzpdDzMEAnERC6UjqrxYrB0tuHMcZArj2E-c_w2yK0RxDtDKI9gmhPIObI3RLxRPTPvqh_RrFZjw</recordid><startdate>197501</startdate><enddate>197501</enddate><creator>Smith, G.</creator><creator>Walford, R.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>197501</creationdate><title>The identification of a minimal feedback vertex set of a directed graph</title><author>Smith, G. ; Walford, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c327t-ed01670c922d1e183e4a09b40b3852f6d13d77fffdff539bac00b71010b57fd93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1975</creationdate><topic>Circuit simulation</topic><topic>Circuit testing</topic><topic>Computational modeling</topic><topic>Feedback</topic><topic>Graph theory</topic><topic>Logic circuits</topic><topic>Logic testing</topic><topic>Pathology</topic><topic>Sequential analysis</topic><topic>Sequential circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Smith, G.</creatorcontrib><creatorcontrib>Walford, R.</creatorcontrib><collection>CrossRef</collection><jtitle>IEEE transactions on circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Smith, G.</au><au>Walford, R.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>The identification of a minimal feedback vertex set of a directed graph</atitle><jtitle>IEEE transactions on circuits and systems</jtitle><stitle>T-CAS</stitle><date>1975-01</date><risdate>1975</risdate><volume>22</volume><issue>1</issue><spage>9</spage><epage>15</epage><pages>9-15</pages><issn>0098-4094</issn><eissn>1558-1276</eissn><coden>ICSYBT</coden><abstract>This paper describes an algorithm for the identification of a minimal feedback vertex set of an arbitrary directed graph. Such a set of vertices has the property that removal of these vertices from the graph eliminates all directed loops. An efficient solution to this identification problem is a familiar unsolved problem of contemporary graph theory. Although pathological examples exist for which excessive computation v2 time may be required, the described algorithm appears to be quite v efficient for large graphs arising in practical applications. The algorithm seems to have great potential in the field of test generation for sequential logic circuits and certain types of simulation algorithms. No attempt is V3 made to impose restrictive conditions on the particular minimum feedback vertex set selected, although such restrictions may at times be desirable. The algorithm has been implemented on an IBM 360/67 and has been successfully applied to practical (logic circuit) problems having in excess of 2500 vertices.</abstract><pub>IEEE</pub><doi>10.1109/TCS.1975.1083961</doi><tpages>7</tpages></addata></record> |
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subjects | Circuit simulation Circuit testing Computational modeling Feedback Graph theory Logic circuits Logic testing Pathology Sequential analysis Sequential circuits |
title | The identification of a minimal feedback vertex set of a directed graph |
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