A 50 Gb/s PAM-4 Transceiver With High-Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links

This paper presents a 50 Gb/s four-level pulse amplitude modulation 4 (PAM-4) wireline transceiver that incorporates a high-swing PAM-4 driver in the transmitter (TX) and an integrator-based baud-rate linear clock and data recovery (IB-CDR) in the receiver (RX). The PAM-4 driver in the TX employs tw...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2024-10, p.1-11
Hauptverfasser:	Sim, Jincheol, Sim, Changmin, Choi, Jonghyuck, Park, Seungwoo, Kim, Seongcheol, Kim, Chulwoo
Format:	Artikel
Sprache:	eng
Schlagworte:	analog equalizer Circuits clock and data recovery (CDR) Clocks Equalizers four-level pulse amplitude modulation (PAM-4) High-speed integrated circuits high-swing driver Logic Optical signal processing Resistors Signal to noise ratio Symbols Threshold voltage Transceivers wireline transceiver
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