Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers
The divider controller in a conventional phase-locked loop fractional- N frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2023-03, Vol.70 (3), p.1057-1070 |
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| container_title | IEEE transactions on circuits and systems. I, Regular papers |
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| creator | Mai, Dawei Kennedy, Michael Peter |
| description | The divider controller in a conventional phase-locked loop fractional- N frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts. |
| doi_str_mv | 10.1109/TCSI.2022.3230634 |
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| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TCSI_2022_3230634</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9999158</ieee_id><sourcerecordid>2779670801</sourcerecordid><originalsourceid>FETCH-LOGICAL-c218t-654d50bcef72b79f2a915530f0fb9da1028c008e410479e8cb27e4cd72ddc823</originalsourceid><addsrcrecordid>eNo9UF1LwzAUDaLgnP4A8aXgc-ZN0jbJ46jODaYDu_fQ5gM7unYmVZi_3pQN78s9F845nHsQuicwIwTk07YoVzMKlM4YZZCz9AJNSJYJDALyyxGnEgtGxTW6CWEHQCUwMkHrzWFo9s2vNcnbvFzi8iN5bn4aY31S9N3g-7aN0PU-WfhKD03fVS1-j4f9-radPiblsRs-bYgOPtyiK1e1wd6d9xRtFy_bYonXm9dVMV9jTYkYcJ6lJoNaW8dpzaWjlYxRGThwtTQVASo0gLApgZRLK3RNuU214dQYLSiboseT7cH3MUUY1K7_9jFYUJRzmfP4M4kscmJp34fgrVMH3-wrf1QE1NiZGjtTY2fq3FnUPJw0jbX2ny_jkEywP1AtZ2c</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2779670801</pqid></control><display><type>article</type><title>Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers</title><source>IEEE Electronic Library (IEL)</source><creator>Mai, Dawei ; Kennedy, Michael Peter</creator><creatorcontrib>Mai, Dawei ; Kennedy, Michael Peter</creatorcontrib><description>The divider controller in a conventional phase-locked loop fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2022.3230634</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Controllers ; Delta-sigma modulation ; Digital electronics ; Dividers ; Frequency synthesizers ; Generators ; MASH-SQ divider controllers ; Modulators ; Multi-stage noise shaping ; Multi-stage noise shaping structure-successive requantizer (MASH-SR) divider controllers ; nonlinearity ; Phase locked loops ; Phase noise ; Quantization (signal) ; quantization noise ; spurious tones ; Synthesis ; Synthesizers</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2023-03, Vol.70 (3), p.1057-1070</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c218t-654d50bcef72b79f2a915530f0fb9da1028c008e410479e8cb27e4cd72ddc823</cites><orcidid>0000-0002-4699-4384 ; 0000-0003-3242-1056</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9999158$$EHTML$$P50$$Gieee$$Hfree_for_read</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54736</link.rule.ids></links><search><creatorcontrib>Mai, Dawei</creatorcontrib><creatorcontrib>Kennedy, Michael Peter</creatorcontrib><title>Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>The divider controller in a conventional phase-locked loop fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.</description><subject>Controllers</subject><subject>Delta-sigma modulation</subject><subject>Digital electronics</subject><subject>Dividers</subject><subject>Frequency synthesizers</subject><subject>Generators</subject><subject>MASH-SQ divider controllers</subject><subject>Modulators</subject><subject>Multi-stage noise shaping</subject><subject>Multi-stage noise shaping structure-successive requantizer (MASH-SR) divider controllers</subject><subject>nonlinearity</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><subject>Quantization (signal)</subject><subject>quantization noise</subject><subject>spurious tones</subject><subject>Synthesis</subject><subject>Synthesizers</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><recordid>eNo9UF1LwzAUDaLgnP4A8aXgc-ZN0jbJ46jODaYDu_fQ5gM7unYmVZi_3pQN78s9F845nHsQuicwIwTk07YoVzMKlM4YZZCz9AJNSJYJDALyyxGnEgtGxTW6CWEHQCUwMkHrzWFo9s2vNcnbvFzi8iN5bn4aY31S9N3g-7aN0PU-WfhKD03fVS1-j4f9-radPiblsRs-bYgOPtyiK1e1wd6d9xRtFy_bYonXm9dVMV9jTYkYcJ6lJoNaW8dpzaWjlYxRGThwtTQVASo0gLApgZRLK3RNuU214dQYLSiboseT7cH3MUUY1K7_9jFYUJRzmfP4M4kscmJp34fgrVMH3-wrf1QE1NiZGjtTY2fq3FnUPJw0jbX2ny_jkEywP1AtZ2c</recordid><startdate>20230301</startdate><enddate>20230301</enddate><creator>Mai, Dawei</creator><creator>Kennedy, Michael Peter</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>ESBDL</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-4699-4384</orcidid><orcidid>https://orcid.org/0000-0003-3242-1056</orcidid></search><sort><creationdate>20230301</creationdate><title>Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers</title><author>Mai, Dawei ; Kennedy, Michael Peter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c218t-654d50bcef72b79f2a915530f0fb9da1028c008e410479e8cb27e4cd72ddc823</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Controllers</topic><topic>Delta-sigma modulation</topic><topic>Digital electronics</topic><topic>Dividers</topic><topic>Frequency synthesizers</topic><topic>Generators</topic><topic>MASH-SQ divider controllers</topic><topic>Modulators</topic><topic>Multi-stage noise shaping</topic><topic>Multi-stage noise shaping structure-successive requantizer (MASH-SR) divider controllers</topic><topic>nonlinearity</topic><topic>Phase locked loops</topic><topic>Phase noise</topic><topic>Quantization (signal)</topic><topic>quantization noise</topic><topic>spurious tones</topic><topic>Synthesis</topic><topic>Synthesizers</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mai, Dawei</creatorcontrib><creatorcontrib>Kennedy, Michael Peter</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE Open Access Journals</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Mai, Dawei</au><au>Kennedy, Michael Peter</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2023-03-01</date><risdate>2023</risdate><volume>70</volume><issue>3</issue><spage>1057</spage><epage>1070</epage><pages>1057-1070</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>The divider controller in a conventional phase-locked loop fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2022.3230634</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0002-4699-4384</orcidid><orcidid>https://orcid.org/0000-0003-3242-1056</orcidid><oa>free_for_read</oa></addata></record> |
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| ispartof | IEEE transactions on circuits and systems. I, Regular papers, 2023-03, Vol.70 (3), p.1057-1070 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Controllers Delta-sigma modulation Digital electronics Dividers Frequency synthesizers Generators MASH-SQ divider controllers Modulators Multi-stage noise shaping Multi-stage noise shaping structure-successive requantizer (MASH-SR) divider controllers nonlinearity Phase locked loops Phase noise Quantization (signal) quantization noise spurious tones Synthesis Synthesizers |
| title | Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T17%3A10%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Optimized%20MASH-SR%20Divider%20Controller%20for%20Fractional-N%20Frequency%20Synthesizers&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20I,%20Regular%20papers&rft.au=Mai,%20Dawei&rft.date=2023-03-01&rft.volume=70&rft.issue=3&rft.spage=1057&rft.epage=1070&rft.pages=1057-1070&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2022.3230634&rft_dat=%3Cproquest_cross%3E2779670801%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2779670801&rft_id=info:pmid/&rft_ieee_id=9999158&rfr_iscdi=true |