A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.

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Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2013-08, Vol.60 (8), p.2009-2017
Hauptverfasser:	Plouchart, J.-O., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., Friedman, D., Ferriss, M., Natarajan, A. S., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B. D., Beakes, M., Babakhani, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitors Field effect transistors Frequency measurement Millimeter wave integrated circuits Phase locked loops Phase noise silicon-on-insulator Tuning Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:	A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.
ISSN:	1549-8328 1558-0806
DOI:	10.1109/TCSI.2013.2265961