A Defect Tolerance Scheme for Nanotechnology Circuits
Lithography-based integrated circuit fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology-based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated us...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2007-11, Vol.54 (11), p.2402-2409 |
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| container_issue | 11 |
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| container_title | IEEE transactions on circuits and systems. I, Regular papers |
| container_volume | 54 |
| creator | Al-Yamani, A.A. Ramsundar, S. Pradhan, D.K. |
| description | Lithography-based integrated circuit fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology-based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques. The algorithm is also consistent in improving the yield through minimizing false rejects as the results show over a large sample. The improvement percentage varies depending on the manufactured switch size and the desired defect-free size with the improvement in efficiency directly proportional to the size of the switch. |
| doi_str_mv | 10.1109/TCSI.2007.907875 |
| format | Article |
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The improvement percentage varies depending on the manufactured switch size and the desired defect-free size with the improvement in efficiency directly proportional to the size of the switch.</description><subject>Algorithms</subject><subject>Circuits</subject><subject>Cross bar switches</subject><subject>defect tolerance</subject><subject>Defects</subject><subject>Fabrication</subject><subject>Fault tolerance</subject><subject>Frequency estimation</subject><subject>Manufacturing</subject><subject>Nanostructure</subject><subject>Nanotechnology</subject><subject>Nanowires</subject><subject>reliability</subject><subject>Self assembly</subject><subject>Silicon</subject><subject>Switches</subject><subject>Tolerances</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kD1PwzAQhi0EEqWwI7FEDDCl2LEd22MVvipVMLTMluucaao0LnYy9N-TKIiBgelueN5Xdw9C1wTPCMHqYV2sFrMMYzFTWEjBT9CEcC5TLHF-OuxMpZJm8hxdxLjDOFOYkgni8-QRHNg2WfsagmksJCu7hT0kzofkzTS-BbttfO0_j0lRBdtVbbxEZ87UEa5-5hR9PD-ti9d0-f6yKObL1FJO27SUxlAGJFd5SSR3XHDpjHF4Q8ACFWAUlIzxDcsyRrmgxPTXWiZU6RSVik7R_dh7CP6rg9jqfRUt1LVpwHdRS5VnmAmMe_LuX5IyprgQWQ_e_gF3vgtN_4WWOVO5zIXoITxCNvgYAzh9CNXehKMmWA-69aBbD7r1qLuP3IyRCgB-cUZ755TQbxjxeVo</recordid><startdate>20071101</startdate><enddate>20071101</enddate><creator>Al-Yamani, A.A.</creator><creator>Ramsundar, S.</creator><creator>Pradhan, D.K.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Al-Yamani, A.A.</au><au>Ramsundar, S.</au><au>Pradhan, D.K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Defect Tolerance Scheme for Nanotechnology Circuits</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2007-11-01</date><risdate>2007</risdate><volume>54</volume><issue>11</issue><spage>2402</spage><epage>2409</epage><pages>2402-2409</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>Lithography-based integrated circuit fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology-based fabrication, which relies on self-assembly of nanotubes or nanowires. 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| ispartof | IEEE transactions on circuits and systems. I, Regular papers, 2007-11, Vol.54 (11), p.2402-2409 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms Circuits Cross bar switches defect tolerance Defects Fabrication Fault tolerance Frequency estimation Manufacturing Nanostructure Nanotechnology Nanowires reliability Self assembly Silicon Switches Tolerances |
| title | A Defect Tolerance Scheme for Nanotechnology Circuits |
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