An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning
The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stag...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2006-12, Vol.53 (12), p.2485-2497 |
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| container_issue | 12 |
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| container_title | IEEE transactions on circuits and systems. 1, Fundamental theory and applications |
| container_volume | 53 |
| creator | Adeniran, O.A. Demosthenous, A. |
| description | The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-mum CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date |
| doi_str_mv | 10.1109/TCSI.2006.885983 |
| format | Article |
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It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-mum CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. 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It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-mum CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date</description><subject>Analog-digital conversion</subject><subject>Analog-to-digital conversion</subject><subject>Architecture</subject><subject>Bit rate</subject><subject>Broadcast technology</subject><subject>CMOS technology</subject><subject>Converters</subject><subject>digital video broadcast-handheld (DVB-H)</subject><subject>Digital video broadcasting</subject><subject>effective resolution bandwidth (ERBW)</subject><subject>Electric potential</subject><subject>Energy consumption</subject><subject>low-voltage circuits</subject><subject>Optimization</subject><subject>Partitioning</subject><subject>pipeline analog-to-digital converter (ADC)</subject><subject>Pipelines</subject><subject>Power consumption</subject><subject>Power measurement</subject><subject>power-efficient ADC</subject><subject>Sampling</subject><subject>Sampling methods</subject><subject>Voltage</subject><issn>1549-8328</issn><issn>1057-7122</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLAzEURgdRsD72gpvgxtXUPGYyybLW-gBBQavLkCY3bco0U5MU0V_vlIoLV_e7cL7L5RTFGcFDQrC8eh2_PAwpxnwoRC0F2ysGpK5FiQXm-9tcyVIwKg6Lo5SWGFOJGRkUbhTQtM1Rl5MAcf5VTpzzxkPI6N1bKK91sJ_e5gV669cOPfs1tD4AGt2M0TT5MEdP6-xX_hssGkWz8BlM3kTdomcds8--Cz10Uhw43SY4_Z3HxfR28jq-Lx-f7h7Go8fSMEpzaS2ZscpSTIQR3FHjNKazpnGNMFRymFW1YQ1Y4KK2nFIG1BmQM6sryy3X7Li43N1dx-5jAymrlU8G2lYH6DZJCSErWteM9-TFP3LZbWLon1OCN1QKWeMewjvIxC6lCE6to1_p-KUIVlvtaqtdbbWrnfa-cr6reAD4wytMOeeE_QBCwX8h</recordid><startdate>20061201</startdate><enddate>20061201</enddate><creator>Adeniran, O.A.</creator><creator>Demosthenous, A.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20061201</creationdate><title>An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning</title><author>Adeniran, O.A. ; Demosthenous, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c322t-dd1b34d2018c86f2cfa02b77f78c296eb45c37ede685d6223e2fce9bda4d6d6a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Analog-digital conversion</topic><topic>Analog-to-digital conversion</topic><topic>Architecture</topic><topic>Bit rate</topic><topic>Broadcast technology</topic><topic>CMOS technology</topic><topic>Converters</topic><topic>digital video broadcast-handheld (DVB-H)</topic><topic>Digital video broadcasting</topic><topic>effective resolution bandwidth (ERBW)</topic><topic>Electric potential</topic><topic>Energy consumption</topic><topic>low-voltage circuits</topic><topic>Optimization</topic><topic>Partitioning</topic><topic>pipeline analog-to-digital converter (ADC)</topic><topic>Pipelines</topic><topic>Power consumption</topic><topic>Power measurement</topic><topic>power-efficient ADC</topic><topic>Sampling</topic><topic>Sampling methods</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Adeniran, O.A.</creatorcontrib><creatorcontrib>Demosthenous, A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Adeniran, O.A.</au><au>Demosthenous, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning</atitle><jtitle>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</jtitle><stitle>TCSI</stitle><date>2006-12-01</date><risdate>2006</risdate><volume>53</volume><issue>12</issue><spage>2485</spage><epage>2497</epage><pages>2485-2497</pages><issn>1549-8328</issn><issn>1057-7122</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. 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| source | IEEE Electronic Library (IEL) |
| subjects | Analog-digital conversion Analog-to-digital conversion Architecture Bit rate Broadcast technology CMOS technology Converters digital video broadcast-handheld (DVB-H) Digital video broadcasting effective resolution bandwidth (ERBW) Electric potential Energy consumption low-voltage circuits Optimization Partitioning pipeline analog-to-digital converter (ADC) Pipelines Power consumption Power measurement power-efficient ADC Sampling Sampling methods Voltage |
| title | An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning |
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