SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit
The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This brief proposes a novel SRAM- and Inverter-based P...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-04, Vol.71 (4), p.2339-2343 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
| container_volume | 71 |
| creator | Ni, Li Wang, Pengjun Zhang, Yuejun Li, Xiangyu Li, Gang Ding, Lin Zhang, Jiliang |
| description | The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This brief proposes a novel SRAM- and Inverter-based PUF (SI PUF) that can operate as either an SRAM PUF or an inverter PUF, depending on the input configuration signal. A zero-overhead bit configuration strategy (BCS) is proposed to enhance the reliability of PUF. Moreover, the working voltage of the sub-threshold level and the well-designed discharge stage ensure that our SI PUF can operate with low power consumption. The tested results of chips fabricated in 40-nm CMOS show that our SI PUF has only 0.0053% of the worst bit error rate (BER) under working conditions of −50 to 125°C and 0.75 to 1.5V, with 0.073/0.042 pJ/bit of power consumption. The low BER and energy overhead illustrate that our SI PUF is more suitable for resource-limited devices compared to DAC 2022 and JSSC 2020. |
| doi_str_mv | 10.1109/TCSII.2023.3339296 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TCSII_2023_3339296</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10354440</ieee_id><sourcerecordid>2995314610</sourcerecordid><originalsourceid>FETCH-LOGICAL-c247t-720ff606303ef5f11b5508cac58be11ba225f2ad866426fee2bbc7e4d9ddeb323</originalsourceid><addsrcrecordid>eNpNkE1Lw0AQhhdRsFb_gHhYEI9JZ7-yXW9taTVSUfqBN8MmmcUUTeomFfz3Jm0PXmbeYd53Bh5CrhmEjIEZrCbLOA45cBEKIQw30QnpMaWGgdCGnXZamkBrqc_JRV1vALgBwXvkfRnT1_Xsno5KulyMnqktcxqXP-gb9MHY1ph3e_pWNB_U0nHR0Kn3lacL2yCtHIUQQIm7fa7VWgzaKjndPg3SorkkZ85-1nh17H2ynk1Xk8dg_vIQT0bzIONSN4Hm4FwEkQCBTjnGUqVgmNlMDVNsJ8u5ctzmwyiSPHKIPE0zjTI3eY6p4KJPbg93t7763mHdJJtq58v2ZcKNUYLJiEHr4gdX5qu69uiSrS--rP9NGCQdx2TPMek4JkeObejmECoQ8V9AKCkliD_yAWiE</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2995314610</pqid></control><display><type>article</type><title>SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit</title><source>IEEE Electronic Library (IEL)</source><creator>Ni, Li ; Wang, Pengjun ; Zhang, Yuejun ; Li, Xiangyu ; Li, Gang ; Ding, Lin ; Zhang, Jiliang</creator><creatorcontrib>Ni, Li ; Wang, Pengjun ; Zhang, Yuejun ; Li, Xiangyu ; Li, Gang ; Ding, Lin ; Zhang, Jiliang</creatorcontrib><description>The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This brief proposes a novel SRAM- and Inverter-based PUF (SI PUF) that can operate as either an SRAM PUF or an inverter PUF, depending on the input configuration signal. A zero-overhead bit configuration strategy (BCS) is proposed to enhance the reliability of PUF. Moreover, the working voltage of the sub-threshold level and the well-designed discharge stage ensure that our SI PUF can operate with low power consumption. The tested results of chips fabricated in 40-nm CMOS show that our SI PUF has only 0.0053% of the worst bit error rate (BER) under working conditions of −50 to 125°C and 0.75 to 1.5V, with 0.073/0.042 pJ/bit of power consumption. The low BER and energy overhead illustrate that our SI PUF is more suitable for resource-limited devices compared to DAC 2022 and JSSC 2020.</description><identifier>ISSN: 1549-7747</identifier><identifier>EISSN: 1558-3791</identifier><identifier>DOI: 10.1109/TCSII.2023.3339296</identifier><identifier>CODEN: ITCSFK</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bit error rate ; Computer architecture ; Configurations ; hardware security ; Inverters ; key generation ; Microprocessors ; Physical unclonable function ; Power consumption ; Power demand ; Power management ; Random access memory ; Reliability ; reliable ; Static random access memory</subject><ispartof>IEEE transactions on circuits and systems. II, Express briefs, 2024-04, Vol.71 (4), p.2339-2343</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c247t-720ff606303ef5f11b5508cac58be11ba225f2ad866426fee2bbc7e4d9ddeb323</cites><orcidid>0000-0001-9133-8282 ; 0009-0002-2299-7246 ; 0000-0002-8698-3217 ; 0000-0002-1461-3719 ; 0000-0001-7287-0695 ; 0000-0001-5538-7829 ; 0000-0003-1132-6332</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10354440$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10354440$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ni, Li</creatorcontrib><creatorcontrib>Wang, Pengjun</creatorcontrib><creatorcontrib>Zhang, Yuejun</creatorcontrib><creatorcontrib>Li, Xiangyu</creatorcontrib><creatorcontrib>Li, Gang</creatorcontrib><creatorcontrib>Ding, Lin</creatorcontrib><creatorcontrib>Zhang, Jiliang</creatorcontrib><title>SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit</title><title>IEEE transactions on circuits and systems. II, Express briefs</title><addtitle>TCSII</addtitle><description>The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This brief proposes a novel SRAM- and Inverter-based PUF (SI PUF) that can operate as either an SRAM PUF or an inverter PUF, depending on the input configuration signal. A zero-overhead bit configuration strategy (BCS) is proposed to enhance the reliability of PUF. Moreover, the working voltage of the sub-threshold level and the well-designed discharge stage ensure that our SI PUF can operate with low power consumption. The tested results of chips fabricated in 40-nm CMOS show that our SI PUF has only 0.0053% of the worst bit error rate (BER) under working conditions of −50 to 125°C and 0.75 to 1.5V, with 0.073/0.042 pJ/bit of power consumption. The low BER and energy overhead illustrate that our SI PUF is more suitable for resource-limited devices compared to DAC 2022 and JSSC 2020.</description><subject>Bit error rate</subject><subject>Computer architecture</subject><subject>Configurations</subject><subject>hardware security</subject><subject>Inverters</subject><subject>key generation</subject><subject>Microprocessors</subject><subject>Physical unclonable function</subject><subject>Power consumption</subject><subject>Power demand</subject><subject>Power management</subject><subject>Random access memory</subject><subject>Reliability</subject><subject>reliable</subject><subject>Static random access memory</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE1Lw0AQhhdRsFb_gHhYEI9JZ7-yXW9taTVSUfqBN8MmmcUUTeomFfz3Jm0PXmbeYd53Bh5CrhmEjIEZrCbLOA45cBEKIQw30QnpMaWGgdCGnXZamkBrqc_JRV1vALgBwXvkfRnT1_Xsno5KulyMnqktcxqXP-gb9MHY1ph3e_pWNB_U0nHR0Kn3lacL2yCtHIUQQIm7fa7VWgzaKjndPg3SorkkZ85-1nh17H2ynk1Xk8dg_vIQT0bzIONSN4Hm4FwEkQCBTjnGUqVgmNlMDVNsJ8u5ctzmwyiSPHKIPE0zjTI3eY6p4KJPbg93t7763mHdJJtq58v2ZcKNUYLJiEHr4gdX5qu69uiSrS--rP9NGCQdx2TPMek4JkeObejmECoQ8V9AKCkliD_yAWiE</recordid><startdate>20240401</startdate><enddate>20240401</enddate><creator>Ni, Li</creator><creator>Wang, Pengjun</creator><creator>Zhang, Yuejun</creator><creator>Li, Xiangyu</creator><creator>Li, Gang</creator><creator>Ding, Lin</creator><creator>Zhang, Jiliang</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-9133-8282</orcidid><orcidid>https://orcid.org/0009-0002-2299-7246</orcidid><orcidid>https://orcid.org/0000-0002-8698-3217</orcidid><orcidid>https://orcid.org/0000-0002-1461-3719</orcidid><orcidid>https://orcid.org/0000-0001-7287-0695</orcidid><orcidid>https://orcid.org/0000-0001-5538-7829</orcidid><orcidid>https://orcid.org/0000-0003-1132-6332</orcidid></search><sort><creationdate>20240401</creationdate><title>SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit</title><author>Ni, Li ; Wang, Pengjun ; Zhang, Yuejun ; Li, Xiangyu ; Li, Gang ; Ding, Lin ; Zhang, Jiliang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c247t-720ff606303ef5f11b5508cac58be11ba225f2ad866426fee2bbc7e4d9ddeb323</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Bit error rate</topic><topic>Computer architecture</topic><topic>Configurations</topic><topic>hardware security</topic><topic>Inverters</topic><topic>key generation</topic><topic>Microprocessors</topic><topic>Physical unclonable function</topic><topic>Power consumption</topic><topic>Power demand</topic><topic>Power management</topic><topic>Random access memory</topic><topic>Reliability</topic><topic>reliable</topic><topic>Static random access memory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ni, Li</creatorcontrib><creatorcontrib>Wang, Pengjun</creatorcontrib><creatorcontrib>Zhang, Yuejun</creatorcontrib><creatorcontrib>Li, Xiangyu</creatorcontrib><creatorcontrib>Li, Gang</creatorcontrib><creatorcontrib>Ding, Lin</creatorcontrib><creatorcontrib>Zhang, Jiliang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ni, Li</au><au>Wang, Pengjun</au><au>Zhang, Yuejun</au><au>Li, Xiangyu</au><au>Li, Gang</au><au>Ding, Lin</au><au>Zhang, Jiliang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2024-04-01</date><risdate>2024</risdate><volume>71</volume><issue>4</issue><spage>2339</spage><epage>2343</epage><pages>2339-2343</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ITCSFK</coden><abstract>The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This brief proposes a novel SRAM- and Inverter-based PUF (SI PUF) that can operate as either an SRAM PUF or an inverter PUF, depending on the input configuration signal. A zero-overhead bit configuration strategy (BCS) is proposed to enhance the reliability of PUF. Moreover, the working voltage of the sub-threshold level and the well-designed discharge stage ensure that our SI PUF can operate with low power consumption. The tested results of chips fabricated in 40-nm CMOS show that our SI PUF has only 0.0053% of the worst bit error rate (BER) under working conditions of −50 to 125°C and 0.75 to 1.5V, with 0.073/0.042 pJ/bit of power consumption. The low BER and energy overhead illustrate that our SI PUF is more suitable for resource-limited devices compared to DAC 2022 and JSSC 2020.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSII.2023.3339296</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0001-9133-8282</orcidid><orcidid>https://orcid.org/0009-0002-2299-7246</orcidid><orcidid>https://orcid.org/0000-0002-8698-3217</orcidid><orcidid>https://orcid.org/0000-0002-1461-3719</orcidid><orcidid>https://orcid.org/0000-0001-7287-0695</orcidid><orcidid>https://orcid.org/0000-0001-5538-7829</orcidid><orcidid>https://orcid.org/0000-0003-1132-6332</orcidid></addata></record> |
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| subjects | Bit error rate Computer architecture Configurations hardware security Inverters key generation Microprocessors Physical unclonable function Power consumption Power demand Power management Random access memory Reliability reliable Static random access memory |
| title | SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit |
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