A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

This brief presents a 32-Gb/s PAM4-Binary bridge for the next-generation memory testing. The bridge incorporates all the required functions to evaluate a high-speed PAM4 memory using a low-speed NRZ tester. The low-speed data transmitted from the NRZ tester to the bridge are converted into high-spee...

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Bibliographische Detailangaben

Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2022-09, Vol.69 (9), p.3749-3753
Hauptverfasser:	Yun, Daeho, Lee, Eonhui, Jung, Woosong, Kim, Kahyun, Beak, Kyung-Min, Kim, Jihee, Lee, Hyun-Bae, Ko, Byeongseon, Choi, Woo-Seok, Jeong, Deog-Kyoon
Format:	Artikel
Sprache:	eng
Schlagworte:	Bridge circuits Cancellation circuits Clocks Equalizers eye-opening monitoring (EOM) High speed Latches Low speed memory tester offset cancellation Optical signal processing PAM-4 PAM4-binary bridge Timing Training
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