A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range
In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the re...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2022-05, Vol.69 (5), p.2428-2432 |
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| creator | Huang, Zizhen Zhong, Jianlin Xie, Chunwei Wu, Ruoyang Zhao, Xiaojin |
| description | In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~ 121.8\times under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests. |
| doi_str_mv | 10.1109/TCSII.2022.3161060 |
| format | Article |
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By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~<inline-formula> <tex-math notation="LaTeX">121.8\times </tex-math></inline-formula> under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests.</description><identifier>ISSN: 1549-7747</identifier><identifier>EISSN: 1558-3791</identifier><identifier>DOI: 10.1109/TCSII.2022.3161060</identifier><identifier>CODEN: ITCSFK</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Autocorrelation functions ; Background noise ; Bit error rate ; Circuits and systems ; CMOS ; Electric potential ; Energy consumption ; energy efficient ; highly reliable ; Inverters ; Physical unclonable function ; Power consumption ; Random access memory ; Reliability ; Reliability aspects ; Schmitt trigger ; Schmitt triggers ; Static random access memory ; ultra-wide supply voltage range ; Voltage</subject><ispartof>IEEE transactions on circuits and systems. II, Express briefs, 2022-05, Vol.69 (5), p.2428-2432</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c210t-2dcc26ab4fcf6e6e74490f9f9fd4cc83d3d775445cf332bf82c891880f094c043</citedby><cites>FETCH-LOGICAL-c210t-2dcc26ab4fcf6e6e74490f9f9fd4cc83d3d775445cf332bf82c891880f094c043</cites><orcidid>0000-0002-9965-3516</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9739775$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9739775$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Huang, Zizhen</creatorcontrib><creatorcontrib>Zhong, Jianlin</creatorcontrib><creatorcontrib>Xie, Chunwei</creatorcontrib><creatorcontrib>Wu, Ruoyang</creatorcontrib><creatorcontrib>Zhao, Xiaojin</creatorcontrib><title>A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range</title><title>IEEE transactions on circuits and systems. II, Express briefs</title><addtitle>TCSII</addtitle><description>In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~<inline-formula> <tex-math notation="LaTeX">121.8\times </tex-math></inline-formula> under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests.</description><subject>Autocorrelation functions</subject><subject>Background noise</subject><subject>Bit error rate</subject><subject>Circuits and systems</subject><subject>CMOS</subject><subject>Electric potential</subject><subject>Energy consumption</subject><subject>energy efficient</subject><subject>highly reliable</subject><subject>Inverters</subject><subject>Physical unclonable function</subject><subject>Power consumption</subject><subject>Random access memory</subject><subject>Reliability</subject><subject>Reliability aspects</subject><subject>Schmitt trigger</subject><subject>Schmitt triggers</subject><subject>Static random access memory</subject><subject>ultra-wide supply voltage range</subject><subject>Voltage</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtPwzAQhC0EEqXwB-BiiXOKX4njY1W1tFIlUB9wjFxnnbpKk-A4h_57UlqhPeweZmZHH0LPlIwoJeptM1kvFiNGGBtxmlCSkBs0oHGcRlwqenu-hYqkFPIePbTtgRCmCGcDlI_x3BX78oRXUDq9KwHrKsfTCnxxiqbWOuOgCnht9kcXAt54VxTg8ed2hmegQ-ddVeBtGbyOvl0OeN01TZ_2VZdBF4BXuirgEd1ZXbbwdN1DtJ1NN5N5tPx4X0zGy8gwSkLEcmNYonfCGptAAlIIRazqJxfGpDznuZSxELGxnLOdTZlJFU1TYokShgg-RK-X3MbXPx20ITvUna_6lxlLYsVFomTcq9hFZXzdth5s1nh31P6UUZKdaWZ_NLMzzexKsze9XEwOAP4NSnLVV-K_7pNwdQ</recordid><startdate>20220501</startdate><enddate>20220501</enddate><creator>Huang, Zizhen</creator><creator>Zhong, Jianlin</creator><creator>Xie, Chunwei</creator><creator>Wu, Ruoyang</creator><creator>Zhao, Xiaojin</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-9965-3516</orcidid></search><sort><creationdate>20220501</creationdate><title>A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range</title><author>Huang, Zizhen ; Zhong, Jianlin ; Xie, Chunwei ; Wu, Ruoyang ; Zhao, Xiaojin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c210t-2dcc26ab4fcf6e6e74490f9f9fd4cc83d3d775445cf332bf82c891880f094c043</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Autocorrelation functions</topic><topic>Background noise</topic><topic>Bit error rate</topic><topic>Circuits and systems</topic><topic>CMOS</topic><topic>Electric potential</topic><topic>Energy consumption</topic><topic>energy efficient</topic><topic>highly reliable</topic><topic>Inverters</topic><topic>Physical unclonable function</topic><topic>Power consumption</topic><topic>Random access memory</topic><topic>Reliability</topic><topic>Reliability aspects</topic><topic>Schmitt trigger</topic><topic>Schmitt triggers</topic><topic>Static random access memory</topic><topic>ultra-wide supply voltage range</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Huang, Zizhen</creatorcontrib><creatorcontrib>Zhong, Jianlin</creatorcontrib><creatorcontrib>Xie, Chunwei</creatorcontrib><creatorcontrib>Wu, Ruoyang</creatorcontrib><creatorcontrib>Zhao, Xiaojin</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Huang, Zizhen</au><au>Zhong, Jianlin</au><au>Xie, Chunwei</au><au>Wu, Ruoyang</au><au>Zhao, Xiaojin</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2022-05-01</date><risdate>2022</risdate><volume>69</volume><issue>5</issue><spage>2428</spage><epage>2432</epage><pages>2428-2432</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ITCSFK</coden><abstract>In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~<inline-formula> <tex-math notation="LaTeX">121.8\times </tex-math></inline-formula> under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSII.2022.3161060</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-9965-3516</orcidid></addata></record> |
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| subjects | Autocorrelation functions Background noise Bit error rate Circuits and systems CMOS Electric potential Energy consumption energy efficient highly reliable Inverters Physical unclonable function Power consumption Random access memory Reliability Reliability aspects Schmitt trigger Schmitt triggers Static random access memory ultra-wide supply voltage range Voltage |
| title | A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range |
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