A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs

This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to ach...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-08, Vol.64 (8), p.927-931
1. Verfasser:	Sakare, Mahendra
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks Decorrelation Delays Generators Integrated circuit testing Latches Logic gates MOS digital circuits multirate systems pseudo-random binary sequence generator (PRBSG) pseudo-random sequences
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!