A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs
This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to ach...
Gespeichert in:
Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-08, Vol.64 (8), p.927-931 |
---|---|
1. Verfasser: | |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 931 |
---|---|
container_issue | 8 |
container_start_page | 927 |
container_title | IEEE transactions on circuits and systems. II, Express briefs |
container_volume | 64 |
creator | Sakare, Mahendra |
description | This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to achieve any desired higher speed multioutput PRBSG in the module. A systematic procedure for designing such a module for a 2 7 -1 PRBSG is discussed. The same technique can be extended for longer length sequences. The proposed architecture is implemented using field-programmable gate array. The quarter-rate implementation shows a 20% and 51% reduction in power and area (number of slices), respectively, when the proposed architecture is compared with the commonly used architecture. The proposed architecture is also synthesized for an integrated circuit implementation in a low-leakage 65-nm CMOS technology. Post-layout simulations show 30.5% and 50.6% reduction in power consumption and area, respectively, when the proposed architecture is compared with the commonly used architecture. |
doi_str_mv | 10.1109/TCSII.2016.2641582 |
format | Article |
fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TCSII_2016_2641582</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7790892</ieee_id><sourcerecordid>10_1109_TCSII_2016_2641582</sourcerecordid><originalsourceid>FETCH-LOGICAL-c267t-74c8d4a9764f8c326d711a59fdb291f596697051716c34376a43f5b27e0e589e3</originalsourceid><addsrcrecordid>eNo9kM1OAjEUhRujiYi-gG76AoP9v9MlEkQSDCgYl5PSuQ01yJBOJ8a3F8S4OucsvrP4CLnlbMA5s_er0XI6HQjGzUAYxXUpzkiPa10WEiw_P3ZlCwAFl-SqbT8YE5ZJ0SMvQ7povjBRt6vpMKGj4xCij7jLh-k3MaPPXULaBOro4vVhSSe4w-Ryk-h7zBv63G1z3G-Rzru873J7TS6C27Z485d98vY4Xo2eitl8Mh0NZ4UXBnIBype1chaMCqWXwtTAudM21GthedDWGAtMc-DGSyXBOCWDXgtAhrq0KPtEnH59ato2Yaj2KX669F1xVh2lVL9SqqOU6k_KAbo7QRER_wEAy0or5A-q01yB</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs</title><source>IEEE Electronic Library (IEL)</source><creator>Sakare, Mahendra</creator><creatorcontrib>Sakare, Mahendra</creatorcontrib><description>This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to achieve any desired higher speed multioutput PRBSG in the module. A systematic procedure for designing such a module for a 2 7 -1 PRBSG is discussed. The same technique can be extended for longer length sequences. The proposed architecture is implemented using field-programmable gate array. The quarter-rate implementation shows a 20% and 51% reduction in power and area (number of slices), respectively, when the proposed architecture is compared with the commonly used architecture. The proposed architecture is also synthesized for an integrated circuit implementation in a low-leakage 65-nm CMOS technology. Post-layout simulations show 30.5% and 50.6% reduction in power consumption and area, respectively, when the proposed architecture is compared with the commonly used architecture.</description><identifier>ISSN: 1549-7747</identifier><identifier>EISSN: 1558-3791</identifier><identifier>DOI: 10.1109/TCSII.2016.2641582</identifier><identifier>CODEN: ICSPE5</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Decorrelation ; Delays ; Generators ; Integrated circuit testing ; Latches ; Logic gates ; MOS digital circuits ; multirate systems ; pseudo-random binary sequence generator (PRBSG) ; pseudo-random sequences</subject><ispartof>IEEE transactions on circuits and systems. II, Express briefs, 2017-08, Vol.64 (8), p.927-931</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c267t-74c8d4a9764f8c326d711a59fdb291f596697051716c34376a43f5b27e0e589e3</citedby><cites>FETCH-LOGICAL-c267t-74c8d4a9764f8c326d711a59fdb291f596697051716c34376a43f5b27e0e589e3</cites><orcidid>0000-0002-5839-3463</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7790892$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,782,786,798,27931,27932,54765</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7790892$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sakare, Mahendra</creatorcontrib><title>A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs</title><title>IEEE transactions on circuits and systems. II, Express briefs</title><addtitle>TCSII</addtitle><description>This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to achieve any desired higher speed multioutput PRBSG in the module. A systematic procedure for designing such a module for a 2 7 -1 PRBSG is discussed. The same technique can be extended for longer length sequences. The proposed architecture is implemented using field-programmable gate array. The quarter-rate implementation shows a 20% and 51% reduction in power and area (number of slices), respectively, when the proposed architecture is compared with the commonly used architecture. The proposed architecture is also synthesized for an integrated circuit implementation in a low-leakage 65-nm CMOS technology. Post-layout simulations show 30.5% and 50.6% reduction in power consumption and area, respectively, when the proposed architecture is compared with the commonly used architecture.</description><subject>Clocks</subject><subject>Decorrelation</subject><subject>Delays</subject><subject>Generators</subject><subject>Integrated circuit testing</subject><subject>Latches</subject><subject>Logic gates</subject><subject>MOS digital circuits</subject><subject>multirate systems</subject><subject>pseudo-random binary sequence generator (PRBSG)</subject><subject>pseudo-random sequences</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1OAjEUhRujiYi-gG76AoP9v9MlEkQSDCgYl5PSuQ01yJBOJ8a3F8S4OucsvrP4CLnlbMA5s_er0XI6HQjGzUAYxXUpzkiPa10WEiw_P3ZlCwAFl-SqbT8YE5ZJ0SMvQ7povjBRt6vpMKGj4xCij7jLh-k3MaPPXULaBOro4vVhSSe4w-Ryk-h7zBv63G1z3G-Rzru873J7TS6C27Z485d98vY4Xo2eitl8Mh0NZ4UXBnIBype1chaMCqWXwtTAudM21GthedDWGAtMc-DGSyXBOCWDXgtAhrq0KPtEnH59ato2Yaj2KX669F1xVh2lVL9SqqOU6k_KAbo7QRER_wEAy0or5A-q01yB</recordid><startdate>201708</startdate><enddate>201708</enddate><creator>Sakare, Mahendra</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0002-5839-3463</orcidid></search><sort><creationdate>201708</creationdate><title>A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs</title><author>Sakare, Mahendra</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c267t-74c8d4a9764f8c326d711a59fdb291f596697051716c34376a43f5b27e0e589e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Clocks</topic><topic>Decorrelation</topic><topic>Delays</topic><topic>Generators</topic><topic>Integrated circuit testing</topic><topic>Latches</topic><topic>Logic gates</topic><topic>MOS digital circuits</topic><topic>multirate systems</topic><topic>pseudo-random binary sequence generator (PRBSG)</topic><topic>pseudo-random sequences</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sakare, Mahendra</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sakare, Mahendra</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2017-08</date><risdate>2017</risdate><volume>64</volume><issue>8</issue><spage>927</spage><epage>931</epage><pages>927-931</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ICSPE5</coden><abstract>This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to achieve any desired higher speed multioutput PRBSG in the module. A systematic procedure for designing such a module for a 2 7 -1 PRBSG is discussed. The same technique can be extended for longer length sequences. The proposed architecture is implemented using field-programmable gate array. The quarter-rate implementation shows a 20% and 51% reduction in power and area (number of slices), respectively, when the proposed architecture is compared with the commonly used architecture. The proposed architecture is also synthesized for an integrated circuit implementation in a low-leakage 65-nm CMOS technology. Post-layout simulations show 30.5% and 50.6% reduction in power consumption and area, respectively, when the proposed architecture is compared with the commonly used architecture.</abstract><pub>IEEE</pub><doi>10.1109/TCSII.2016.2641582</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-5839-3463</orcidid></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1549-7747 |
ispartof | IEEE transactions on circuits and systems. II, Express briefs, 2017-08, Vol.64 (8), p.927-931 |
issn | 1549-7747 1558-3791 |
language | eng |
recordid | cdi_crossref_primary_10_1109_TCSII_2016_2641582 |
source | IEEE Electronic Library (IEL) |
subjects | Clocks Decorrelation Delays Generators Integrated circuit testing Latches Logic gates MOS digital circuits multirate systems pseudo-random binary sequence generator (PRBSG) pseudo-random sequences |
title | A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-05T14%3A15%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Power%20and%20Area%20Efficient%20Architecture%20of%20a%20PRBS%20Generator%20With%20Multiple%20Outputs&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20II,%20Express%20briefs&rft.au=Sakare,%20Mahendra&rft.date=2017-08&rft.volume=64&rft.issue=8&rft.spage=927&rft.epage=931&rft.pages=927-931&rft.issn=1549-7747&rft.eissn=1558-3791&rft.coden=ICSPE5&rft_id=info:doi/10.1109/TCSII.2016.2641582&rft_dat=%3Ccrossref_RIE%3E10_1109_TCSII_2016_2641582%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=7790892&rfr_iscdi=true |