Optimal Single Constant Multiplication Using Ternary Adders
The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As m...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2018-07, Vol.65 (7), p.928-932 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 932 |
|---|---|
| container_issue | 7 |
| container_start_page | 928 |
| container_title | IEEE transactions on circuits and systems. II, Express briefs |
| container_volume | 65 |
| creator | Kumm, Martin Gustafsson, Oscar Garrido, Mario Zipf, Peter |
| description | The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts. |
| doi_str_mv | 10.1109/TCSII.2016.2631630 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TCSII_2016_2631630</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7752883</ieee_id><sourcerecordid>2061455084</sourcerecordid><originalsourceid>FETCH-LOGICAL-c333t-a8e034c8bc2699f655569b4429206079060651e5fe8a1e0962024c7b3df6d5493</originalsourceid><addsrcrecordid>eNo9UFtLwzAUDqLgnP4BfSn43Jl7Gnwa9TaY7GGbryFt05FR25qkyP69mR17OefA-W58ANwjOEMIyqdNvl4sZhgiPsOcIE7gBZggxrKUCIkujzeVqRBUXIMb7_cQYgkJnoDnVR_st26StW13jUnyrvVBtyH5HJpg-8aWOtiuTbY-_pONca12h2ReVcb5W3BV68abu9Oegu3b6yb_SJer90U-X6YlISSkOjOQ0DIrSsylrDljjMuCUiwx5FDIODhDhtUm08hAyTHEtBQFqWpexdhkCtJR1_-afihU72Jid1CdturFfs1V53aqsYNCVPIsi_jHEd-77mcwPqh9N8TgjVfREVHGYEYjCo-o0nXeO1OfdRFUx1LVf6nqWKo6lRpJDyPJGmPOBCEYjr7kDwRkcUo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2061455084</pqid></control><display><type>article</type><title>Optimal Single Constant Multiplication Using Ternary Adders</title><source>IEEE Electronic Library (IEL)</source><creator>Kumm, Martin ; Gustafsson, Oscar ; Garrido, Mario ; Zipf, Peter</creator><creatorcontrib>Kumm, Martin ; Gustafsson, Oscar ; Garrido, Mario ; Zipf, Peter</creatorcontrib><description>The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.</description><identifier>ISSN: 1549-7747</identifier><identifier>ISSN: 1558-3791</identifier><identifier>EISSN: 1558-3791</identifier><identifier>DOI: 10.1109/TCSII.2016.2631630</identifier><identifier>CODEN: ICSPE5</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Adders ; Arithmetic ; circuit optimization ; circuits ; Complexity theory ; digital arithmetic ; Field programmable gate arrays ; field-programmable gate arrays (FPGAs) ; fixed-point arithmetic optimization ; Gate arrays ; mathematics ; Multiplication ; Multiplication & division ; multiplying circuits ; Optimization ; optimization methods ; Programmable logic controllers ; Signal processing algorithms ; Topology</subject><ispartof>IEEE transactions on circuits and systems. II, Express briefs, 2018-07, Vol.65 (7), p.928-932</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c333t-a8e034c8bc2699f655569b4429206079060651e5fe8a1e0962024c7b3df6d5493</citedby><cites>FETCH-LOGICAL-c333t-a8e034c8bc2699f655569b4429206079060651e5fe8a1e0962024c7b3df6d5493</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7752883$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,314,780,784,796,885,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7752883$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-149688$$DView record from Swedish Publication Index$$Hfree_for_read</backlink></links><search><creatorcontrib>Kumm, Martin</creatorcontrib><creatorcontrib>Gustafsson, Oscar</creatorcontrib><creatorcontrib>Garrido, Mario</creatorcontrib><creatorcontrib>Zipf, Peter</creatorcontrib><title>Optimal Single Constant Multiplication Using Ternary Adders</title><title>IEEE transactions on circuits and systems. II, Express briefs</title><addtitle>TCSII</addtitle><description>The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.</description><subject>Adders</subject><subject>Arithmetic</subject><subject>circuit optimization</subject><subject>circuits</subject><subject>Complexity theory</subject><subject>digital arithmetic</subject><subject>Field programmable gate arrays</subject><subject>field-programmable gate arrays (FPGAs)</subject><subject>fixed-point arithmetic optimization</subject><subject>Gate arrays</subject><subject>mathematics</subject><subject>Multiplication</subject><subject>Multiplication & division</subject><subject>multiplying circuits</subject><subject>Optimization</subject><subject>optimization methods</subject><subject>Programmable logic controllers</subject><subject>Signal processing algorithms</subject><subject>Topology</subject><issn>1549-7747</issn><issn>1558-3791</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9UFtLwzAUDqLgnP4BfSn43Jl7Gnwa9TaY7GGbryFt05FR25qkyP69mR17OefA-W58ANwjOEMIyqdNvl4sZhgiPsOcIE7gBZggxrKUCIkujzeVqRBUXIMb7_cQYgkJnoDnVR_st26StW13jUnyrvVBtyH5HJpg-8aWOtiuTbY-_pONca12h2ReVcb5W3BV68abu9Oegu3b6yb_SJer90U-X6YlISSkOjOQ0DIrSsylrDljjMuCUiwx5FDIODhDhtUm08hAyTHEtBQFqWpexdhkCtJR1_-afihU72Jid1CdturFfs1V53aqsYNCVPIsi_jHEd-77mcwPqh9N8TgjVfREVHGYEYjCo-o0nXeO1OfdRFUx1LVf6nqWKo6lRpJDyPJGmPOBCEYjr7kDwRkcUo</recordid><startdate>20180701</startdate><enddate>20180701</enddate><creator>Kumm, Martin</creator><creator>Gustafsson, Oscar</creator><creator>Garrido, Mario</creator><creator>Zipf, Peter</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>ADTPV</scope><scope>AOWAS</scope><scope>DG8</scope></search><sort><creationdate>20180701</creationdate><title>Optimal Single Constant Multiplication Using Ternary Adders</title><author>Kumm, Martin ; Gustafsson, Oscar ; Garrido, Mario ; Zipf, Peter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c333t-a8e034c8bc2699f655569b4429206079060651e5fe8a1e0962024c7b3df6d5493</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Adders</topic><topic>Arithmetic</topic><topic>circuit optimization</topic><topic>circuits</topic><topic>Complexity theory</topic><topic>digital arithmetic</topic><topic>Field programmable gate arrays</topic><topic>field-programmable gate arrays (FPGAs)</topic><topic>fixed-point arithmetic optimization</topic><topic>Gate arrays</topic><topic>mathematics</topic><topic>Multiplication</topic><topic>Multiplication & division</topic><topic>multiplying circuits</topic><topic>Optimization</topic><topic>optimization methods</topic><topic>Programmable logic controllers</topic><topic>Signal processing algorithms</topic><topic>Topology</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kumm, Martin</creatorcontrib><creatorcontrib>Gustafsson, Oscar</creatorcontrib><creatorcontrib>Garrido, Mario</creatorcontrib><creatorcontrib>Zipf, Peter</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>SwePub</collection><collection>SwePub Articles</collection><collection>SWEPUB Linköpings universitet</collection><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kumm, Martin</au><au>Gustafsson, Oscar</au><au>Garrido, Mario</au><au>Zipf, Peter</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Optimal Single Constant Multiplication Using Ternary Adders</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2018-07-01</date><risdate>2018</risdate><volume>65</volume><issue>7</issue><spage>928</spage><epage>932</epage><pages>928-932</pages><issn>1549-7747</issn><issn>1558-3791</issn><eissn>1558-3791</eissn><coden>ICSPE5</coden><abstract>The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSII.2016.2631630</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1549-7747 |
| ispartof | IEEE transactions on circuits and systems. II, Express briefs, 2018-07, Vol.65 (7), p.928-932 |
| issn | 1549-7747 1558-3791 1558-3791 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_TCSII_2016_2631630 |
| source | IEEE Electronic Library (IEL) |
| subjects | Adders Arithmetic circuit optimization circuits Complexity theory digital arithmetic Field programmable gate arrays field-programmable gate arrays (FPGAs) fixed-point arithmetic optimization Gate arrays mathematics Multiplication Multiplication & division multiplying circuits Optimization optimization methods Programmable logic controllers Signal processing algorithms Topology |
| title | Optimal Single Constant Multiplication Using Ternary Adders |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T23%3A20%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Optimal%20Single%20Constant%20Multiplication%20Using%20Ternary%20Adders&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20II,%20Express%20briefs&rft.au=Kumm,%20Martin&rft.date=2018-07-01&rft.volume=65&rft.issue=7&rft.spage=928&rft.epage=932&rft.pages=928-932&rft.issn=1549-7747&rft.eissn=1558-3791&rft.coden=ICSPE5&rft_id=info:doi/10.1109/TCSII.2016.2631630&rft_dat=%3Cproquest_RIE%3E2061455084%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2061455084&rft_id=info:pmid/&rft_ieee_id=7752883&rfr_iscdi=true |