A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting

We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a G m -C preamplifier. This approach allows us to relax precision and enhance speed during noncritical decision...

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Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-02, Vol.64 (2), p.116-120
Hauptverfasser:	Kramer, Martin, Janssen, Erwin, Doris, Kostas, Murmann, Boris
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog-to-digital converter (ADC) complementary metal-oxide semiconductor (CMOS) Delays Gain Gears Latches Redundancy Signal to noise ratio successive approximation register (SAR)
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