A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting
We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a G m -C preamplifier. This approach allows us to relax precision and enhance speed during noncritical decision...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-02, Vol.64 (2), p.116-120 |
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| container_end_page | 120 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
| container_volume | 64 |
| creator | Kramer, Martin Janssen, Erwin Doris, Kostas Murmann, Boris |
| description | We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a G m -C preamplifier. This approach allows us to relax precision and enhance speed during noncritical decisions, leading to an aggregate speed-up of 22% compared to a conventional design. The ADC operates at 30 MS/s, achieves a peak signal-to-noise and distortion ratio of 77.2 dB, and consumes 38 mW from 1.2 V/2.5 V supplies, corresponding to a Schreier FOM of 163.1 dB (161.6 dB at Nyquist). The proof-of-concept converter is implemented in a 40-nm LP complementary metal-oxide semiconductor process and occupies 0.24 mm 2 . |
| doi_str_mv | 10.1109/TCSII.2016.2554858 |
| format | Article |
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| subjects | Analog-to-digital converter (ADC) complementary metal-oxide semiconductor (CMOS) Delays Gain Gears Latches Redundancy Signal to noise ratio successive approximation register (SAR) |
| title | A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting |
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