Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme

This brief presents a time-to-digital converter (TDC) with a three-level conversion scheme based on a dual delay-locked loop (DLL) structure. The linear-feedback-shift-register counter is implemented for measurement range extension, and a differential delay cell is adopted for time resolution improv...

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Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-02, Vol.64 (2), p.181-185
Hauptverfasser:	Wu, Jin, Jiang, Qi, Song, Ke, Zheng, Lixia, Sun, Dongchen, Sun, Weifeng
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks Delay-locked loop (DLL) Delays Logic gates measurement range Measurement uncertainty Quantization (signal) Signal resolution time resolution time-to-digital converter (TDC)
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