Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme
This brief presents a time-to-digital converter (TDC) with a three-level conversion scheme based on a dual delay-locked loop (DLL) structure. The linear-feedback-shift-register counter is implemented for measurement range extension, and a differential delay cell is adopted for time resolution improv...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-02, Vol.64 (2), p.181-185 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
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| creator | Wu, Jin Jiang, Qi Song, Ke Zheng, Lixia Sun, Dongchen Sun, Weifeng |
| description | This brief presents a time-to-digital converter (TDC) with a three-level conversion scheme based on a dual delay-locked loop (DLL) structure. The linear-feedback-shift-register counter is implemented for measurement range extension, and a differential delay cell is adopted for time resolution improvement. Furthermore, the DLL is applied to improve the stability of the multiphase clock frequency. The test chip is designed and fabricated in a Taiwan Semiconductor Manufacturing Company 0.35-μm CMOS process. With an input reference clock of 40 MHz, the total 15-bit three-level TDC can realize a 3-μs maximum range and a 476-ps resolution. The differential nonlinearity is less than ±0.65 LSB, and the integral nonlinearity is within -1.35 LSB to +1.4 LSB. |
| doi_str_mv | 10.1109/TCSII.2016.2554818 |
| format | Article |
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| source | IEEE Electronic Library (IEL) |
| subjects | Clocks Delay-locked loop (DLL) Delays Logic gates measurement range Measurement uncertainty Quantization (signal) Signal resolution time resolution time-to-digital converter (TDC) |
| title | Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme |
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