Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity

Two design techniques are proposed for high-throughput low-density parity-check (LDPC) decoders. A broadcasting technique mitigates routing congestion by reducing the total global wirelength. An interlacing technique increases the decoder throughput by processing two consecutive frames simultaneousl...

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Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2008-01, Vol.55 (1), p.74-78
Hauptverfasser:	Darabiha, A., Carusone, A.C., Kschischang, F.R.
Format:	Artikel
Sprache:	eng
Schlagworte:	10-GB Ethernet Bit error rate Blocking Broadcasting channel coding Circuits Counting decoder architectures Decoders Design engineering Gates Hardware Iterative decoding iterative message-passing low-density parity-check (LDPC) codes Memory management Parallel architectures Parity check codes Routing Throughput Very large scale integration very-large-scale integration (VLSI)
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