Failure Analysis and Experimental Verification for Through-Silicon-via Underfill Dispensing on 3-D Chip Stack Package

In this paper, through-silicon-via (TSV) dispensing is introduced to address the underfill challenge for a 3-D chip stack package. An edge flood failure would form if the underfill flow breaks through the planar sidewalls of a 3-D package. The edge flood failure could lead to an incomplete underfill...

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Veröffentlicht in:	IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2015-10, Vol.5 (10), p.1525-1532
Hauptverfasser:	Fuliang Le, Lee, Shi-Wei Ricky, Lo, Jeffery C. C., Chaoran Yang
Format:	Artikel
Sprache:	eng
Schlagworte:	3D die stack Assembly Atmospheric modeling dispensing Mathematical model Silicon Stacking Substrates Through-silicon vias underfill
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