Compact Functional Testing for Neuromorphic Computing Circuits

We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count di...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2023-07, Vol.42 (7), p.2391-2403
Hauptverfasser:	El-Sayed, Sarah A., Spyrou, Theofilos, Camunas-Mesa, Luis A., Stratigopoulos, Haralampos-G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Artificial Intelligence Circuit faults Computational modeling Computer Aided Engineering Computer Science Engineering Sciences Fault detection Fault modeling fault simulation Functional testing Hardware Hardware acceleration Micro and nanotechnologies Microelectronics Neural networks Neuromorphic computing Neurons Perturbation spiking neural networks (SNNs) Test pattern generators Testing
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