Compact Functional Testing for Neuromorphic Computing Circuits

We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count di...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2023-07, Vol.42 (7), p.2391-2403
Hauptverfasser: El-Sayed, Sarah A., Spyrou, Theofilos, Camunas-Mesa, Luis A., Stratigopoulos, Haralampos-G.
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container_issue 7
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container_title IEEE transactions on computer-aided design of integrated circuits and systems
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creator El-Sayed, Sarah A.
Spyrou, Theofilos
Camunas-Mesa, Luis A.
Stratigopoulos, Haralampos-G.
description We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassified with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near-perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modeled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.
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fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TCAD_2022_3223843</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9956887</ieee_id><sourcerecordid>2828000471</sourcerecordid><originalsourceid>FETCH-LOGICAL-c322t-7252cd1b40b1b39a81f9852d8b9a75e4b0684fe40a613783fae78ea80b08dfff3</originalsourceid><addsrcrecordid>eNo9kE9LAzEQxYMoWKsfQLwsePKwdfJnm-QilNVaoeilnkM2TWxK26zJruC3d9ctPQ3M_N5j3kPoFsMEY5CPq3L2PCFAyIQSQgWjZ2iEJeU5wwU-RyMgXOQAHC7RVUpbAMwKIkfoqQz7Wpsmm7cH0_hw0LtsZVPjD1-ZCzF7t20M-xDrjTdZz7b_p9JH0_omXaMLp3fJ3hznGH3OX1blIl9-vL6Vs2VuuneanJOCmDWuGFS4olIL7KQoyFpUUvPCsgqmgjnLQE8x5YI6bbmwWkAFYu2co2P0MPhu9E7V0e91_FVBe7WYLVW_AyoKybH8wR17P7B1DN9tl0VtQxu7YEkRQQQAMN5TeKBMDClF6062GFRfqeorVX2l6lhpp7kbNN5ae-KlLKZCcPoHWbFw1w</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2828000471</pqid></control><display><type>article</type><title>Compact Functional Testing for Neuromorphic Computing Circuits</title><source>IEEE Electronic Library (IEL)</source><creator>El-Sayed, Sarah A. ; Spyrou, Theofilos ; Camunas-Mesa, Luis A. ; Stratigopoulos, Haralampos-G.</creator><creatorcontrib>El-Sayed, Sarah A. ; Spyrou, Theofilos ; Camunas-Mesa, Luis A. ; Stratigopoulos, Haralampos-G.</creatorcontrib><description>We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassified with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near-perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modeled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2022.3223843</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Artificial Intelligence ; Circuit faults ; Computational modeling ; Computer Aided Engineering ; Computer Science ; Engineering Sciences ; Fault detection ; Fault modeling ; fault simulation ; Functional testing ; Hardware ; Hardware acceleration ; Micro and nanotechnologies ; Microelectronics ; Neural networks ; Neuromorphic computing ; Neurons ; Perturbation ; spiking neural networks (SNNs) ; Test pattern generators ; Testing</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2023-07, Vol.42 (7), p.2391-2403</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c322t-7252cd1b40b1b39a81f9852d8b9a75e4b0684fe40a613783fae78ea80b08dfff3</cites><orcidid>0000-0002-4694-458X ; 0000-0002-3425-854X ; 0000-0002-9943-5607</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9956887$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,314,780,784,796,885,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9956887$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://hal.science/hal-03859719$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>El-Sayed, Sarah A.</creatorcontrib><creatorcontrib>Spyrou, Theofilos</creatorcontrib><creatorcontrib>Camunas-Mesa, Luis A.</creatorcontrib><creatorcontrib>Stratigopoulos, Haralampos-G.</creatorcontrib><title>Compact Functional Testing for Neuromorphic Computing Circuits</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassified with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near-perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modeled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.</description><subject>Artificial Intelligence</subject><subject>Circuit faults</subject><subject>Computational modeling</subject><subject>Computer Aided Engineering</subject><subject>Computer Science</subject><subject>Engineering Sciences</subject><subject>Fault detection</subject><subject>Fault modeling</subject><subject>fault simulation</subject><subject>Functional testing</subject><subject>Hardware</subject><subject>Hardware acceleration</subject><subject>Micro and nanotechnologies</subject><subject>Microelectronics</subject><subject>Neural networks</subject><subject>Neuromorphic computing</subject><subject>Neurons</subject><subject>Perturbation</subject><subject>spiking neural networks (SNNs)</subject><subject>Test pattern generators</subject><subject>Testing</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE9LAzEQxYMoWKsfQLwsePKwdfJnm-QilNVaoeilnkM2TWxK26zJruC3d9ctPQ3M_N5j3kPoFsMEY5CPq3L2PCFAyIQSQgWjZ2iEJeU5wwU-RyMgXOQAHC7RVUpbAMwKIkfoqQz7Wpsmm7cH0_hw0LtsZVPjD1-ZCzF7t20M-xDrjTdZz7b_p9JH0_omXaMLp3fJ3hznGH3OX1blIl9-vL6Vs2VuuneanJOCmDWuGFS4olIL7KQoyFpUUvPCsgqmgjnLQE8x5YI6bbmwWkAFYu2co2P0MPhu9E7V0e91_FVBe7WYLVW_AyoKybH8wR17P7B1DN9tl0VtQxu7YEkRQQQAMN5TeKBMDClF6062GFRfqeorVX2l6lhpp7kbNN5ae-KlLKZCcPoHWbFw1w</recordid><startdate>20230701</startdate><enddate>20230701</enddate><creator>El-Sayed, Sarah A.</creator><creator>Spyrou, Theofilos</creator><creator>Camunas-Mesa, Luis A.</creator><creator>Stratigopoulos, Haralampos-G.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>1XC</scope><scope>VOOES</scope><orcidid>https://orcid.org/0000-0002-4694-458X</orcidid><orcidid>https://orcid.org/0000-0002-3425-854X</orcidid><orcidid>https://orcid.org/0000-0002-9943-5607</orcidid></search><sort><creationdate>20230701</creationdate><title>Compact Functional Testing for Neuromorphic Computing Circuits</title><author>El-Sayed, Sarah A. ; Spyrou, Theofilos ; Camunas-Mesa, Luis A. ; Stratigopoulos, Haralampos-G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c322t-7252cd1b40b1b39a81f9852d8b9a75e4b0684fe40a613783fae78ea80b08dfff3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Artificial Intelligence</topic><topic>Circuit faults</topic><topic>Computational modeling</topic><topic>Computer Aided Engineering</topic><topic>Computer Science</topic><topic>Engineering Sciences</topic><topic>Fault detection</topic><topic>Fault modeling</topic><topic>fault simulation</topic><topic>Functional testing</topic><topic>Hardware</topic><topic>Hardware acceleration</topic><topic>Micro and nanotechnologies</topic><topic>Microelectronics</topic><topic>Neural networks</topic><topic>Neuromorphic computing</topic><topic>Neurons</topic><topic>Perturbation</topic><topic>spiking neural networks (SNNs)</topic><topic>Test pattern generators</topic><topic>Testing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>El-Sayed, Sarah A.</creatorcontrib><creatorcontrib>Spyrou, Theofilos</creatorcontrib><creatorcontrib>Camunas-Mesa, Luis A.</creatorcontrib><creatorcontrib>Stratigopoulos, Haralampos-G.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Hyper Article en Ligne (HAL)</collection><collection>Hyper Article en Ligne (HAL) (Open Access)</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>El-Sayed, Sarah A.</au><au>Spyrou, Theofilos</au><au>Camunas-Mesa, Luis A.</au><au>Stratigopoulos, Haralampos-G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Compact Functional Testing for Neuromorphic Computing Circuits</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2023-07-01</date><risdate>2023</risdate><volume>42</volume><issue>7</issue><spage>2391</spage><epage>2403</epage><pages>2391-2403</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassified with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near-perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modeled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2022.3223843</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-4694-458X</orcidid><orcidid>https://orcid.org/0000-0002-3425-854X</orcidid><orcidid>https://orcid.org/0000-0002-9943-5607</orcidid><oa>free_for_read</oa></addata></record>
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subjects Artificial Intelligence
Circuit faults
Computational modeling
Computer Aided Engineering
Computer Science
Engineering Sciences
Fault detection
Fault modeling
fault simulation
Functional testing
Hardware
Hardware acceleration
Micro and nanotechnologies
Microelectronics
Neural networks
Neuromorphic computing
Neurons
Perturbation
spiking neural networks (SNNs)
Test pattern generators
Testing
title Compact Functional Testing for Neuromorphic Computing Circuits
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T01%3A23%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Compact%20Functional%20Testing%20for%20Neuromorphic%20Computing%20Circuits&rft.jtitle=IEEE%20transactions%20on%20computer-aided%20design%20of%20integrated%20circuits%20and%20systems&rft.au=El-Sayed,%20Sarah%20A.&rft.date=2023-07-01&rft.volume=42&rft.issue=7&rft.spage=2391&rft.epage=2403&rft.pages=2391-2403&rft.issn=0278-0070&rft.eissn=1937-4151&rft.coden=ITCSDI&rft_id=info:doi/10.1109/TCAD.2022.3223843&rft_dat=%3Cproquest_RIE%3E2828000471%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2828000471&rft_id=info:pmid/&rft_ieee_id=9956887&rfr_iscdi=true