FLASH: Fast, Parallel, and Accurate Simulator for HLS

A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL simulation environment often creates a barrier for those who are not field-programmable gate array (FPGA) experts. Moreover, such a low-level simulation takes a long time to complete. Software HLS simulators can hel...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2020-12, Vol.39 (12), p.4828-4841
Hauptverfasser:	Choi, Young-Kyu, Chi, Yuze, Wang, Jie, Cong, Jason
Format:	Artikel
Sprache:	eng
Schlagworte:	Acceleration Estimation Field programmable gate arrays Field-programmable gate array (FPGA) Force High level synthesis high-level synthesis (HLS) Semantics Simulation simulation acceleration Simulators Software source-to-source transformation
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