FLASH: Fast, Parallel, and Accurate Simulator for HLS
A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL simulation environment often creates a barrier for those who are not field-programmable gate array (FPGA) experts. Moreover, such a low-level simulation takes a long time to complete. Software HLS simulators can hel...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2020-12, Vol.39 (12), p.4828-4841 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Choi, Young-Kyu Chi, Yuze Wang, Jie Cong, Jason |
| description | A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL simulation environment often creates a barrier for those who are not field-programmable gate array (FPGA) experts. Moreover, such a low-level simulation takes a long time to complete. Software HLS simulators can help bridge this gap and accelerate the simulation process; but their shortcoming is that they do not provide performance estimation. To make matters worse, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve these performance estimation and correctness problems while maintaining the high speed of software simulators, this article proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. The experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation. |
| doi_str_mv | 10.1109/TCAD.2020.2970597 |
| format | Article |
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| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4828-4841 |
| issn | 0278-0070 1937-4151 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Acceleration Estimation Field programmable gate arrays Field-programmable gate array (FPGA) Force High level synthesis high-level synthesis (HLS) Semantics Simulation simulation acceleration Simulators Software source-to-source transformation |
| title | FLASH: Fast, Parallel, and Accurate Simulator for HLS |
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