A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits
Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost assoc...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2019-10, Vol.38 (10), p.1942-1955 |
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| container_end_page | 1955 |
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| container_issue | 10 |
| container_start_page | 1942 |
| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 38 |
| creator | Koneru, Abhishek Kannan, Sukeshwar Chakrabarty, Krishnendu |
| description | Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of interlayer via density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs. The proposed technique provides test schedules with minimum test time under power consumption and probe pad constraints. |
| doi_str_mv | 10.1109/TCAD.2018.2864290 |
| format | Article |
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The proposed technique provides test schedules with minimum test time under power consumption and probe pad constraints.</description><subject>Cost modeling</subject><subject>Density</subject><subject>design-for-test</subject><subject>Integrated circuits</subject><subject>Interconnections</subject><subject>Interlayers</subject><subject>monolithic 3-D (M3D)</subject><subject>Optimization</subject><subject>Optimization techniques</subject><subject>Pins</subject><subject>Power consumption</subject><subject>Schedules</subject><subject>Scheduling</subject><subject>Silicon</subject><subject>Stress</subject><subject>test scheduling</subject><subject>Testing</subject><subject>Three-dimensional displays</subject><subject>Transistors</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9UMlOwzAQtRBIlOUDEBdLnFM8trP4WFKWSkUcWs6R60xaVyEptnPo3-Mu4jTzNG8ZPUIegI0BmHpelpPpmDMoxrzIJFfsgoxAiTyRkMIlGTGeFwljObsmN95vGQOZcjUiYUKn6O26S5reJUv0gS76dgi27-iL9ljTuEyxtkaHCI6Eud6j81R3Z7wwG6yH1nZrGk3oZ9_1rQ0ba6hIpnTWBVy7o7q0zgw2-Dty1ejW4_153pLvt9dl-ZHMv95n5WSeGK5ESFKUIBgIw9KmQMgzhVo1mikppW5MytPMAFfpyqDIdL2SesU0FwKzJoMaC3FLnk6-O9f_DvHVatsProuRFY8JKs_TQkYWnFjG9d47bKqdsz_a7Stg1aHc6lBudSi3OpcbNY8njUXEf34RbwBc_AHI63U5</recordid><startdate>20191001</startdate><enddate>20191001</enddate><creator>Koneru, Abhishek</creator><creator>Kannan, Sukeshwar</creator><creator>Chakrabarty, Krishnendu</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2019-10, Vol.38 (10), p.1942-1955 |
| issn | 0278-0070 1937-4151 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_TCAD_2018_2864290 |
| source | IEEE Electronic Library (IEL) |
| subjects | Cost modeling Density design-for-test Integrated circuits Interconnections Interlayers monolithic 3-D (M3D) Optimization Optimization techniques Pins Power consumption Schedules Scheduling Silicon Stress test scheduling Testing Three-dimensional displays Transistors |
| title | A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits |
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