A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization
Task mapping has been a hot topic in multiprocessor system-on-chip software design for decades. During the mapping process, load balance (LB) and communication optimization have been two important performance optimization factors. This paper studies the relations between LB, interprocessor communica...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2019-09, Vol.38 (9), p.1744-1757 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Huang, Kai Zhang, Xiaomeng Zheng, Dandan Yu, Min Jiang, Xiaowen Yan, Xiaolang de Brisolara, Lisane B. Jerraya, Ahmed Amine |
| description | Task mapping has been a hot topic in multiprocessor system-on-chip software design for decades. During the mapping process, load balance (LB) and communication optimization have been two important performance optimization factors. This paper studies the relations between LB, interprocessor communications, and communication pipeline technique during the mapping process, and proposes an integer linear programming (ILP)-based static task mapping approach, which considers both LB and communication optimization. The approach consists of an optimized ILP model for task mapping with fewer variables compared to previous ILP mapping works. Moreover, to enhance the scalability of the ILP task mapping, the task-processor-cluster algorithm is proposed to reduce the scale of the task graph and the number of processors and then solve the coarse-grained input by the ILP mapping. To increase the adaptability of the ILP task mapping, the improved augmented \epsilon -constraint method is further integrated with the ILP formulations to select the best mapping for different applications. Experimental results on a 2/4/8/16/24-CPU platform of both synthetic and real-life benchmarks demonstrate the efficiency of the proposed approach. |
| doi_str_mv | 10.1109/TCAD.2018.2859400 |
| format | Article |
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During the mapping process, load balance (LB) and communication optimization have been two important performance optimization factors. This paper studies the relations between LB, interprocessor communications, and communication pipeline technique during the mapping process, and proposes an integer linear programming (ILP)-based static task mapping approach, which considers both LB and communication optimization. The approach consists of an optimized ILP model for task mapping with fewer variables compared to previous ILP mapping works. Moreover, to enhance the scalability of the ILP task mapping, the task-processor-cluster algorithm is proposed to reduce the scale of the task graph and the number of processors and then solve the coarse-grained input by the ILP mapping. To increase the adaptability of the ILP task mapping, the improved augmented <inline-formula> <tex-math notation="LaTeX">\epsilon </tex-math></inline-formula>-constraint method is further integrated with the ILP formulations to select the best mapping for different applications. Experimental results on a 2/4/8/16/24-CPU platform of both synthetic and real-life benchmarks demonstrate the efficiency of the proposed approach.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2018.2859400</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Clustering algorithms ; Communication ; Formulations ; Graph partitioning ; integer linear programming (ILP) ; Integer programming ; Linear programming ; Load balancing ; Load modeling ; Mapping ; Microprocessors ; multiobjective optimization ; Multiprocessing ; multiprocessor system-on-chip (MPSoC) ; Optimization ; Partitioning algorithms ; Pipelines ; Program processors ; System on chip ; Task analysis ; task mapping</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2019-09, Vol.38 (9), p.1744-1757</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-ff309f03ba103d32cc66c492225031226a3c54977ddb14473e961271da8ae11d3</citedby><cites>FETCH-LOGICAL-c293t-ff309f03ba103d32cc66c492225031226a3c54977ddb14473e961271da8ae11d3</cites><orcidid>0000-0002-2593-2969</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8419265$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8419265$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Huang, Kai</creatorcontrib><creatorcontrib>Zhang, Xiaomeng</creatorcontrib><creatorcontrib>Zheng, Dandan</creatorcontrib><creatorcontrib>Yu, Min</creatorcontrib><creatorcontrib>Jiang, Xiaowen</creatorcontrib><creatorcontrib>Yan, Xiaolang</creatorcontrib><creatorcontrib>de Brisolara, Lisane B.</creatorcontrib><creatorcontrib>Jerraya, Ahmed Amine</creatorcontrib><title>A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>Task mapping has been a hot topic in multiprocessor system-on-chip software design for decades. During the mapping process, load balance (LB) and communication optimization have been two important performance optimization factors. This paper studies the relations between LB, interprocessor communications, and communication pipeline technique during the mapping process, and proposes an integer linear programming (ILP)-based static task mapping approach, which considers both LB and communication optimization. The approach consists of an optimized ILP model for task mapping with fewer variables compared to previous ILP mapping works. Moreover, to enhance the scalability of the ILP task mapping, the task-processor-cluster algorithm is proposed to reduce the scale of the task graph and the number of processors and then solve the coarse-grained input by the ILP mapping. To increase the adaptability of the ILP task mapping, the improved augmented <inline-formula> <tex-math notation="LaTeX">\epsilon </tex-math></inline-formula>-constraint method is further integrated with the ILP formulations to select the best mapping for different applications. Experimental results on a 2/4/8/16/24-CPU platform of both synthetic and real-life benchmarks demonstrate the efficiency of the proposed approach.</description><subject>Algorithms</subject><subject>Clustering algorithms</subject><subject>Communication</subject><subject>Formulations</subject><subject>Graph partitioning</subject><subject>integer linear programming (ILP)</subject><subject>Integer programming</subject><subject>Linear programming</subject><subject>Load balancing</subject><subject>Load modeling</subject><subject>Mapping</subject><subject>Microprocessors</subject><subject>multiobjective optimization</subject><subject>Multiprocessing</subject><subject>multiprocessor system-on-chip (MPSoC)</subject><subject>Optimization</subject><subject>Partitioning algorithms</subject><subject>Pipelines</subject><subject>Program processors</subject><subject>System on chip</subject><subject>Task analysis</subject><subject>task mapping</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtPwzAQhC0EEqXwAxAXS5xTdu28fEzDq1KrVmo5R67tQEoThzg9gMR_J2kqTqtZzcxqP0JuESaIIB42afI4YYDxhMWB8AHOyAgFjzwfAzwnI2BR7AFEcEmunNsBoB8wMSK_CV0ruZfbvaGy0jTRsm6PajZfeVPpTLer68ZK9UFz29CNdJ90Ieu6qN6prehitbYpTW3lCm2afjm3UtNp11mpoTO1ZXmoCiXbogss67Yoi5-juCYXudw7c3OaY_L2_LRJX7358mWWJnNPMcFbL885iBz4ViJwzZlSYah8wRgLgCNjoeQq8EUUab1F34-4ESGyCLWMpUHUfEzuh97uka-DcW22s4em6k5mrAPDRQws7lw4uFRjnWtMntVNUcrmO0PIespZTznrKWcnyl3mbsgUxph_f-yjYGHA_wCD-Xc0</recordid><startdate>20190901</startdate><enddate>20190901</enddate><creator>Huang, Kai</creator><creator>Zhang, Xiaomeng</creator><creator>Zheng, Dandan</creator><creator>Yu, Min</creator><creator>Jiang, Xiaowen</creator><creator>Yan, Xiaolang</creator><creator>de Brisolara, Lisane B.</creator><creator>Jerraya, Ahmed Amine</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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During the mapping process, load balance (LB) and communication optimization have been two important performance optimization factors. This paper studies the relations between LB, interprocessor communications, and communication pipeline technique during the mapping process, and proposes an integer linear programming (ILP)-based static task mapping approach, which considers both LB and communication optimization. The approach consists of an optimized ILP model for task mapping with fewer variables compared to previous ILP mapping works. Moreover, to enhance the scalability of the ILP task mapping, the task-processor-cluster algorithm is proposed to reduce the scale of the task graph and the number of processors and then solve the coarse-grained input by the ILP mapping. To increase the adaptability of the ILP task mapping, the improved augmented <inline-formula> <tex-math notation="LaTeX">\epsilon </tex-math></inline-formula>-constraint method is further integrated with the ILP formulations to select the best mapping for different applications. Experimental results on a 2/4/8/16/24-CPU platform of both synthetic and real-life benchmarks demonstrate the efficiency of the proposed approach.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2018.2859400</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0002-2593-2969</orcidid></addata></record> |
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| subjects | Algorithms Clustering algorithms Communication Formulations Graph partitioning integer linear programming (ILP) Integer programming Linear programming Load balancing Load modeling Mapping Microprocessors multiobjective optimization Multiprocessing multiprocessor system-on-chip (MPSoC) Optimization Partitioning algorithms Pipelines Program processors System on chip Task analysis task mapping |
| title | A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization |
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