A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling

Near-threshold and sub-threshold voltage designs have been identified as possible solutions to overcome the limitations introduced by energy consumption in modern very large scale integration circuits. However, as we approach sub-10 nm transistor technology, aggressive voltage, and gate length scali...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2018-03, Vol.37 (3), p.643-656
Hauptverfasser:	Donato, Marco, Bahar, R. Iris, Patterson, William R., Zaslavsky, Alexander
Format:	Artikel
Sprache:	eng
Schlagworte:	Computational modeling Integrated circuit modeling Logic gates Mathematical model Random telegraph signal (RTS) noise reliability simulation single-event transients Thermal noise Transient analysis Transistors
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