Aliasing Reduction in Accumulator-Based Response Verification

One of the well-known problems in response verification is aliasing, i.e., the event that a series of responses containing errors results in a signature equal to that of the error-free response sequence. In this paper, we propose a scheme to reduce aliasing in accumulator-based response verification...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2014-11, Vol.33 (11), p.1746-1750
1. Verfasser:	Voyiatzis, Ioannis
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Aliasing Built-in self-test Circuit faults Compaction Computer aided design Design engineering Hardware Monitoring Probability Reduction Series (mathematics) Signatures
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