Cell-Aware Test

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generat...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2014-09, Vol.33 (9), p.1396-1409
Hauptverfasser:	Hapke, Friedrich, Redemund, Wilfried, Glowatz, Andreas, Rajski, Janusz, Reese, Michael, Hustava, Marek, Keim, Martin, Schloeffel, Juergen, Fast, Anja
Format:	Artikel
Sprache:	eng
Schlagworte:	Automatic test pattern generation Automotive components Bridge circuits Computer aided design Defects Design engineering Failure analysis Layout Libraries Logic gates Mathematical models Microprocessors Resistors Transistors
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!