Generalized Power-Delay Metrics in Deep Submicron CMOS Designs
Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90-nm technology with higher leakage currents, it is appropriate to revisit existing desig...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2007-01, Vol.26 (1), p.183-189 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Sengupta, D. Saleh, R. |
| description | Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90-nm technology with higher leakage currents, it is appropriate to revisit existing design metrics. In this paper, a reevaluation of the metrics is carried out, and a generalized set of metrics is proposed. Supply voltage (V DD ) and threshold voltage (V T ) scaling are two popular approaches to power reduction. As such, the effects on power and frequency are analyzed, and the feasible region of operation is identified in the V DD versus V T plane. A fundamental relationship is established between the optimal operating points and the generalized design metrics. The initial findings also indicate that some designs may have a higher percentage of leakage than expected to achieve overall power reduction, running somewhat counter to conventional wisdom |
| doi_str_mv | 10.1109/TCAD.2006.883926 |
| format | Article |
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The initial findings also indicate that some designs may have a higher percentage of leakage than expected to achieve overall power reduction, running somewhat counter to conventional wisdom</description><subject>Appropriate technology</subject><subject>CMOS</subject><subject>Deep submicron (DSM)</subject><subject>Delay</subject><subject>Design engineering</subject><subject>Electric potential</subject><subject>Electricity supply industry</subject><subject>Frequency</subject><subject>Leakage current</subject><subject>metrics</subject><subject>Microprocessors</subject><subject>Optimization</subject><subject>Power dissipation</subject><subject>Power supplies</subject><subject>Reduction</subject><subject>Running</subject><subject>system-on-chip (SOC)</subject><subject>Threshold voltage</subject><subject>Very large scale integration</subject><subject>very-large-scale integration (VLSI)</subject><subject>Voltage</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkM9LwzAUx4MoOKd3wUvx4qnzJWmz5CKMTqewMWHzHLL0VTK6diYrY_71tlQ8eHrw-Hzfjw8htxRGlIJ6XGeT6YgBiJGUXDFxRgZU8XGc0JSekwGwsYwBxnBJrkLYAtAkZWpAnmZYoTel-8Y8eq-P6OMpluYULfDgnQ2Rq6Ip4j5aNZuds76uomyxXLW94D6rcE0uClMGvPmtQ_Lx8rzOXuP5cvaWTeax5YwdYtMuQ8tygVxCKoFagZtCpqawNmFCFRYQVC6s4cYKMAWKHISBxDIqQSV8SB76uXtffzUYDnrngsWyNBXWTdBSghCCQkfe_yO3deOr9jgtRQKpUAAtBD3UPhSCx0LvvdsZf9IUdKdTdzp1p1P3OtvIXR9xiPiHJ8BVSjn_AXR9bwk</recordid><startdate>200701</startdate><enddate>200701</enddate><creator>Sengupta, D.</creator><creator>Saleh, R.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2007-01, Vol.26 (1), p.183-189 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Appropriate technology CMOS Deep submicron (DSM) Delay Design engineering Electric potential Electricity supply industry Frequency Leakage current metrics Microprocessors Optimization Power dissipation Power supplies Reduction Running system-on-chip (SOC) Threshold voltage Very large scale integration very-large-scale integration (VLSI) Voltage |
| title | Generalized Power-Delay Metrics in Deep Submicron CMOS Designs |
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