PART: Programmable Array Testing Based on a Partitioning Algorithm
PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout i...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1984-04, Vol.3 (2), p.142-149 |
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| container_end_page | 149 |
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| container_issue | 2 |
| container_start_page | 142 |
| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 3 |
| creator | Somenzi, F. Silvano Gai Mezzalama, M. Prinetto, P. |
| description | PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made. |
| doi_str_mv | 10.1109/TCAD.1984.1270068 |
| format | Article |
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To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.1984.1270068</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Design automation ; Electronics ; Equations ; Exact sciences and technology ; Integrated circuits ; Partitioning algorithms ; Power generation ; Programmable logic arrays ; Research and development ; Semiconductor electronics. Microelectronics. Optoelectronics. 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To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.</description><subject>Applied sciences</subject><subject>Design automation</subject><subject>Electronics</subject><subject>Equations</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Partitioning algorithms</subject><subject>Power generation</subject><subject>Programmable logic arrays</subject><subject>Research and development</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon</subject><subject>System testing</subject><subject>Test pattern generators</subject><subject>Very large scale integration</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1984</creationdate><recordtype>article</recordtype><recordid>eNpFkEtLw0AUhQdRsFZ_gLjJQtyl3jt5zMRdWp9QsEhcDzfTSR3Jo86ki_57E1p0deHwnY_LYewaYYYI2X2xyB9nmMl4hlwApPKETTCLRBhjgqdsAlzIEEDAObvw_hsA44RnEzZf5R_FQ7By3cZR01BZmyB3jvZBYXxv200wJ2_WQdcGFKzI9ba3XTvmeb3pnO2_mkt2VlHtzdXxTtnn81OxeA2X7y9vi3wZ6ohHfVjC2hiIqlQKg1pLLUupUVKJEmJTCqFjqdOY0IiKgIwY8oQgRZJVpmUVTdndwbt13c9u-E411mtT19SabucVl0nMk0gOIB5A7TrvnanU1tmG3F4hqHEtNa6lxrXUca2hc3uUk9dUV45abf1fMUs5Cp4O2M0Bs8aYf-1R8gvm9XIh</recordid><startdate>19840401</startdate><enddate>19840401</enddate><creator>Somenzi, F.</creator><creator>Silvano Gai</creator><creator>Mezzalama, M.</creator><creator>Prinetto, P.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19840401</creationdate><title>PART: Programmable Array Testing Based on a Partitioning Algorithm</title><author>Somenzi, F. ; Silvano Gai ; Mezzalama, M. ; Prinetto, P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c323t-b0dee03f687e1cc8c8b8c18ab1804eb77c48c64a1e7fa0ae71805a061a8f9c8f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1984</creationdate><topic>Applied sciences</topic><topic>Design automation</topic><topic>Electronics</topic><topic>Equations</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Partitioning algorithms</topic><topic>Power generation</topic><topic>Programmable logic arrays</topic><topic>Research and development</topic><topic>Semiconductor electronics. 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Solid state devices</topic><topic>Silicon</topic><topic>System testing</topic><topic>Test pattern generators</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Somenzi, F.</creatorcontrib><creatorcontrib>Silvano Gai</creatorcontrib><creatorcontrib>Mezzalama, M.</creatorcontrib><creatorcontrib>Prinetto, P.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Somenzi, F.</au><au>Silvano Gai</au><au>Mezzalama, M.</au><au>Prinetto, P.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>PART: Programmable Array Testing Based on a Partitioning Algorithm</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1984-04-01</date><risdate>1984</risdate><volume>3</volume><issue>2</issue><spage>142</spage><epage>149</epage><pages>142-149</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TCAD.1984.1270068</doi><tpages>8</tpages></addata></record> |
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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 1984-04, Vol.3 (2), p.142-149 |
| issn | 0278-0070 1937-4151 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_TCAD_1984_1270068 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Design automation Electronics Equations Exact sciences and technology Integrated circuits Partitioning algorithms Power generation Programmable logic arrays Research and development Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon System testing Test pattern generators Very large scale integration |
| title | PART: Programmable Array Testing Based on a Partitioning Algorithm |
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