Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake
Skylake's core, processor graphics, and system on chip were designed to meet a demanding set of requirements for a wide range of power-performance points. Its coherent fabric was designed to provide high-memory bandwidth from multiple memory sources. Skylake's power management, which inclu...
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| Veröffentlicht in: | IEEE MICRO 2017-03, Vol.37 (2), p.52-62 |
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| creator | Doweck, Jack Kao, Wen-Fu Lu, Allen Kuan-yu Mandelblat, Julius Rahatekar, Anirudha Rappoport, Lihu Rotem, Efraim Yasin, Ahmad Yoaz, Adi |
| description | Skylake's core, processor graphics, and system on chip were designed to meet a demanding set of requirements for a wide range of power-performance points. Its coherent fabric was designed to provide high-memory bandwidth from multiple memory sources. Skylake's power management, which includes Intel Speed Shift technology, was designed to provide the largest dynamic power range among prior Intel processors. The Intel Architecture core delivers higher power efficiency, higher frequency, and a wider dynamic power range, supporting smaller form factors. Skylake's Gen9 graphics provides new features designed to maximize energy efficiency and bring the best visual experience for gaming and media. Skylake offers a rich performance monitoring unit that enhances software developers' ability to optimize their applications. |
| doi_str_mv | 10.1109/MM.2017.38 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_MM_2017_38</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7924286</ieee_id><sourcerecordid>1898381217</sourcerecordid><originalsourceid>FETCH-LOGICAL-c279t-fb863870c400912a24f9238a3f5fdcdfeab042fac717d820c82137281fa060d43</originalsourceid><addsrcrecordid>eNo9kL1PwzAQxS0EEqWwsLJEYkNKOZ_T2mZDFZSipgzAbLnOWU0_ErBdof73pCpiuuH99N67x9g1hwHnoO_LcoDA5UCoE9bjWsi84IU4ZT1AiTmXAs_ZRYwrABgiqB57nTaxrigbpWU-oYaCTXXbZNMm0SYbt4Eesjn9ZGXtQmuDW9aJXNoF6rSK8rndUpW9r_cbu6ZLdubtJtLV3-2zz-enj_FLPnubTMePs9yh1Cn3CzUSSoIrADRHi4XXKJQVfugrV3myCyjQWye5rBSCU8iFRMW9hRFUheiz26PvV2i_dxSTWbW70HSRhiuthOLYPdpnd0eqKx5jIG--Qr21YW84mMNWpizNYSsjVAffHOGaiP5BqbHAruwvKcxi2w</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1898381217</pqid></control><display><type>article</type><title>Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake</title><source>IEEE Electronic Library (IEL)</source><creator>Doweck, Jack ; Kao, Wen-Fu ; Lu, Allen Kuan-yu ; Mandelblat, Julius ; Rahatekar, Anirudha ; Rappoport, Lihu ; Rotem, Efraim ; Yasin, Ahmad ; Yoaz, Adi</creator><creatorcontrib>Doweck, Jack ; Kao, Wen-Fu ; Lu, Allen Kuan-yu ; Mandelblat, Julius ; Rahatekar, Anirudha ; Rappoport, Lihu ; Rotem, Efraim ; Yasin, Ahmad ; Yoaz, Adi</creatorcontrib><description>Skylake's core, processor graphics, and system on chip were designed to meet a demanding set of requirements for a wide range of power-performance points. Its coherent fabric was designed to provide high-memory bandwidth from multiple memory sources. Skylake's power management, which includes Intel Speed Shift technology, was designed to provide the largest dynamic power range among prior Intel processors. The Intel Architecture core delivers higher power efficiency, higher frequency, and a wider dynamic power range, supporting smaller form factors. Skylake's Gen9 graphics provides new features designed to maximize energy efficiency and bring the best visual experience for gaming and media. Skylake offers a rich performance monitoring unit that enhances software developers' ability to optimize their applications.</description><identifier>ISSN: 0272-1732</identifier><identifier>EISSN: 1937-4143</identifier><identifier>DOI: 10.1109/MM.2017.38</identifier><identifier>CODEN: IEMIDZ</identifier><language>eng</language><publisher>Los Alamitos: IEEE</publisher><subject>Bandwidth ; Central Processing Unit ; Computer architecture ; Dynamic range ; eDRAM ; Energy management ; Form factors ; GPU ; Graphics ; Graphics processing units ; Intel Speed Shift ; Microarchitecture ; Microprocessors ; Performance evaluation ; performance measurements ; performance monitoring ; Ports (Computers) ; Power efficiency ; Power management ; Processors ; Product development ; Skylake ; System on chip ; Turbo</subject><ispartof>IEEE MICRO, 2017-03, Vol.37 (2), p.52-62</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c279t-fb863870c400912a24f9238a3f5fdcdfeab042fac717d820c82137281fa060d43</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7924286$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7924286$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Doweck, Jack</creatorcontrib><creatorcontrib>Kao, Wen-Fu</creatorcontrib><creatorcontrib>Lu, Allen Kuan-yu</creatorcontrib><creatorcontrib>Mandelblat, Julius</creatorcontrib><creatorcontrib>Rahatekar, Anirudha</creatorcontrib><creatorcontrib>Rappoport, Lihu</creatorcontrib><creatorcontrib>Rotem, Efraim</creatorcontrib><creatorcontrib>Yasin, Ahmad</creatorcontrib><creatorcontrib>Yoaz, Adi</creatorcontrib><title>Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake</title><title>IEEE MICRO</title><addtitle>MM</addtitle><description>Skylake's core, processor graphics, and system on chip were designed to meet a demanding set of requirements for a wide range of power-performance points. Its coherent fabric was designed to provide high-memory bandwidth from multiple memory sources. Skylake's power management, which includes Intel Speed Shift technology, was designed to provide the largest dynamic power range among prior Intel processors. The Intel Architecture core delivers higher power efficiency, higher frequency, and a wider dynamic power range, supporting smaller form factors. Skylake's Gen9 graphics provides new features designed to maximize energy efficiency and bring the best visual experience for gaming and media. Skylake offers a rich performance monitoring unit that enhances software developers' ability to optimize their applications.</description><subject>Bandwidth</subject><subject>Central Processing Unit</subject><subject>Computer architecture</subject><subject>Dynamic range</subject><subject>eDRAM</subject><subject>Energy management</subject><subject>Form factors</subject><subject>GPU</subject><subject>Graphics</subject><subject>Graphics processing units</subject><subject>Intel Speed Shift</subject><subject>Microarchitecture</subject><subject>Microprocessors</subject><subject>Performance evaluation</subject><subject>performance measurements</subject><subject>performance monitoring</subject><subject>Ports (Computers)</subject><subject>Power efficiency</subject><subject>Power management</subject><subject>Processors</subject><subject>Product development</subject><subject>Skylake</subject><subject>System on chip</subject><subject>Turbo</subject><issn>0272-1732</issn><issn>1937-4143</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kL1PwzAQxS0EEqWwsLJEYkNKOZ_T2mZDFZSipgzAbLnOWU0_ErBdof73pCpiuuH99N67x9g1hwHnoO_LcoDA5UCoE9bjWsi84IU4ZT1AiTmXAs_ZRYwrABgiqB57nTaxrigbpWU-oYaCTXXbZNMm0SYbt4Eesjn9ZGXtQmuDW9aJXNoF6rSK8rndUpW9r_cbu6ZLdubtJtLV3-2zz-enj_FLPnubTMePs9yh1Cn3CzUSSoIrADRHi4XXKJQVfugrV3myCyjQWye5rBSCU8iFRMW9hRFUheiz26PvV2i_dxSTWbW70HSRhiuthOLYPdpnd0eqKx5jIG--Qr21YW84mMNWpizNYSsjVAffHOGaiP5BqbHAruwvKcxi2w</recordid><startdate>20170301</startdate><enddate>20170301</enddate><creator>Doweck, Jack</creator><creator>Kao, Wen-Fu</creator><creator>Lu, Allen Kuan-yu</creator><creator>Mandelblat, Julius</creator><creator>Rahatekar, Anirudha</creator><creator>Rappoport, Lihu</creator><creator>Rotem, Efraim</creator><creator>Yasin, Ahmad</creator><creator>Yoaz, Adi</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20170301</creationdate><title>Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake</title><author>Doweck, Jack ; Kao, Wen-Fu ; Lu, Allen Kuan-yu ; Mandelblat, Julius ; Rahatekar, Anirudha ; Rappoport, Lihu ; Rotem, Efraim ; Yasin, Ahmad ; Yoaz, Adi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c279t-fb863870c400912a24f9238a3f5fdcdfeab042fac717d820c82137281fa060d43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Bandwidth</topic><topic>Central Processing Unit</topic><topic>Computer architecture</topic><topic>Dynamic range</topic><topic>eDRAM</topic><topic>Energy management</topic><topic>Form factors</topic><topic>GPU</topic><topic>Graphics</topic><topic>Graphics processing units</topic><topic>Intel Speed Shift</topic><topic>Microarchitecture</topic><topic>Microprocessors</topic><topic>Performance evaluation</topic><topic>performance measurements</topic><topic>performance monitoring</topic><topic>Ports (Computers)</topic><topic>Power efficiency</topic><topic>Power management</topic><topic>Processors</topic><topic>Product development</topic><topic>Skylake</topic><topic>System on chip</topic><topic>Turbo</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Doweck, Jack</creatorcontrib><creatorcontrib>Kao, Wen-Fu</creatorcontrib><creatorcontrib>Lu, Allen Kuan-yu</creatorcontrib><creatorcontrib>Mandelblat, Julius</creatorcontrib><creatorcontrib>Rahatekar, Anirudha</creatorcontrib><creatorcontrib>Rappoport, Lihu</creatorcontrib><creatorcontrib>Rotem, Efraim</creatorcontrib><creatorcontrib>Yasin, Ahmad</creatorcontrib><creatorcontrib>Yoaz, Adi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE MICRO</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Doweck, Jack</au><au>Kao, Wen-Fu</au><au>Lu, Allen Kuan-yu</au><au>Mandelblat, Julius</au><au>Rahatekar, Anirudha</au><au>Rappoport, Lihu</au><au>Rotem, Efraim</au><au>Yasin, Ahmad</au><au>Yoaz, Adi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake</atitle><jtitle>IEEE MICRO</jtitle><stitle>MM</stitle><date>2017-03-01</date><risdate>2017</risdate><volume>37</volume><issue>2</issue><spage>52</spage><epage>62</epage><pages>52-62</pages><issn>0272-1732</issn><eissn>1937-4143</eissn><coden>IEMIDZ</coden><abstract>Skylake's core, processor graphics, and system on chip were designed to meet a demanding set of requirements for a wide range of power-performance points. Its coherent fabric was designed to provide high-memory bandwidth from multiple memory sources. Skylake's power management, which includes Intel Speed Shift technology, was designed to provide the largest dynamic power range among prior Intel processors. The Intel Architecture core delivers higher power efficiency, higher frequency, and a wider dynamic power range, supporting smaller form factors. Skylake's Gen9 graphics provides new features designed to maximize energy efficiency and bring the best visual experience for gaming and media. Skylake offers a rich performance monitoring unit that enhances software developers' ability to optimize their applications.</abstract><cop>Los Alamitos</cop><pub>IEEE</pub><doi>10.1109/MM.2017.38</doi><tpages>11</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Bandwidth Central Processing Unit Computer architecture Dynamic range eDRAM Energy management Form factors GPU Graphics Graphics processing units Intel Speed Shift Microarchitecture Microprocessors Performance evaluation performance measurements performance monitoring Ports (Computers) Power efficiency Power management Processors Product development Skylake System on chip Turbo |
| title | Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T10%3A11%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Inside%206th-Generation%20Intel%20Core:%20New%20Microarchitecture%20Code-Named%20Skylake&rft.jtitle=IEEE%20MICRO&rft.au=Doweck,%20Jack&rft.date=2017-03-01&rft.volume=37&rft.issue=2&rft.spage=52&rft.epage=62&rft.pages=52-62&rft.issn=0272-1732&rft.eissn=1937-4143&rft.coden=IEMIDZ&rft_id=info:doi/10.1109/MM.2017.38&rft_dat=%3Cproquest_RIE%3E1898381217%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1898381217&rft_id=info:pmid/&rft_ieee_id=7924286&rfr_iscdi=true |