Efficient Spatial Processing Element Control via Triggered Instructions
In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without exp...
Gespeichert in:
Veröffentlicht in: | IEEE MICRO 2014-05, Vol.34 (3), p.120-137 |
---|---|
Hauptverfasser: | , , , , , , , , , , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 137 |
---|---|
container_issue | 3 |
container_start_page | 120 |
container_title | IEEE MICRO |
container_volume | 34 |
creator | Parashar, Angshuman Pellauer, Michael Adler, Michael Ahsan, Bushra Crago, Neal Lustig, Daniel Pavlov, Vladimir Zhai, Antonia Gambhir, Mohit Jaleel, Aamer Allmon, Randy Rayess, Rachid Maresh, Stephen Emer, Joel |
description | In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture. |
doi_str_mv | 10.1109/MM.2014.14 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_MM_2014_14</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6762794</ieee_id><sourcerecordid>3351625391</sourcerecordid><originalsourceid>FETCH-LOGICAL-c279t-8475246b10c434bf40818161adaf364357fae290480d7bb3318659312ec6b6153</originalsourceid><addsrcrecordid>eNo9kMFKAzEURYMoWKsbt24G3AlT85JMMllKqbXQQcG6Dpk0KSnTSU1Swb_vlIqrt7iHex8HoXvAEwAsn5tmQjCwCbALNAJJRcmA0Us0wkSQEgQl1-gmpS3GuCK4HqH5zDlvvO1z8bnX2euu-IjB2JR8vylmnd2domnocwxd8eN1sYp-s7HRrotFn3I8mOxDn27RldNdsnd_d4y-Xmer6Vu5fJ8vpi_L0hAhc1kzURHGW8CGUdY6hmuogYNea0c5o5Vw2hKJWY3Xom0phZpXkgKxhrccKjpGj-fefQzfB5uy2oZD7IdJBRXDUoCUYqCezpSJIaVondpHv9PxVwFWJ1GqadRJlBrsjNHDGfbW2n-QCz58zOgRTclh3A</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1540971997</pqid></control><display><type>article</type><title>Efficient Spatial Processing Element Control via Triggered Instructions</title><source>IEEE Electronic Library (IEL)</source><creator>Parashar, Angshuman ; Pellauer, Michael ; Adler, Michael ; Ahsan, Bushra ; Crago, Neal ; Lustig, Daniel ; Pavlov, Vladimir ; Zhai, Antonia ; Gambhir, Mohit ; Jaleel, Aamer ; Allmon, Randy ; Rayess, Rachid ; Maresh, Stephen ; Emer, Joel</creator><creatorcontrib>Parashar, Angshuman ; Pellauer, Michael ; Adler, Michael ; Ahsan, Bushra ; Crago, Neal ; Lustig, Daniel ; Pavlov, Vladimir ; Zhai, Antonia ; Gambhir, Mohit ; Jaleel, Aamer ; Allmon, Randy ; Rayess, Rachid ; Maresh, Stephen ; Emer, Joel</creatorcontrib><description>In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.</description><identifier>ISSN: 0272-1732</identifier><identifier>EISSN: 1937-4143</identifier><identifier>DOI: 10.1109/MM.2014.14</identifier><identifier>CODEN: IEMIDZ</identifier><language>eng</language><publisher>Los Alamitos: IEEE</publisher><subject>Arrays ; Computer architecture ; Computer programming ; Control systems ; Field programmable gate arrays ; Hardware ; high performance computing ; Instruction sets ; networking ; Parallel processing ; processing element ; Programming ; Radiation detectors ; spatial parallelism ; triggered instruction</subject><ispartof>IEEE MICRO, 2014-05, Vol.34 (3), p.120-137</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) May-Jun 2014</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c279t-8475246b10c434bf40818161adaf364357fae290480d7bb3318659312ec6b6153</citedby><cites>FETCH-LOGICAL-c279t-8475246b10c434bf40818161adaf364357fae290480d7bb3318659312ec6b6153</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6762794$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6762794$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Parashar, Angshuman</creatorcontrib><creatorcontrib>Pellauer, Michael</creatorcontrib><creatorcontrib>Adler, Michael</creatorcontrib><creatorcontrib>Ahsan, Bushra</creatorcontrib><creatorcontrib>Crago, Neal</creatorcontrib><creatorcontrib>Lustig, Daniel</creatorcontrib><creatorcontrib>Pavlov, Vladimir</creatorcontrib><creatorcontrib>Zhai, Antonia</creatorcontrib><creatorcontrib>Gambhir, Mohit</creatorcontrib><creatorcontrib>Jaleel, Aamer</creatorcontrib><creatorcontrib>Allmon, Randy</creatorcontrib><creatorcontrib>Rayess, Rachid</creatorcontrib><creatorcontrib>Maresh, Stephen</creatorcontrib><creatorcontrib>Emer, Joel</creatorcontrib><title>Efficient Spatial Processing Element Control via Triggered Instructions</title><title>IEEE MICRO</title><addtitle>MM</addtitle><description>In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.</description><subject>Arrays</subject><subject>Computer architecture</subject><subject>Computer programming</subject><subject>Control systems</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>high performance computing</subject><subject>Instruction sets</subject><subject>networking</subject><subject>Parallel processing</subject><subject>processing element</subject><subject>Programming</subject><subject>Radiation detectors</subject><subject>spatial parallelism</subject><subject>triggered instruction</subject><issn>0272-1732</issn><issn>1937-4143</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMFKAzEURYMoWKsbt24G3AlT85JMMllKqbXQQcG6Dpk0KSnTSU1Swb_vlIqrt7iHex8HoXvAEwAsn5tmQjCwCbALNAJJRcmA0Us0wkSQEgQl1-gmpS3GuCK4HqH5zDlvvO1z8bnX2euu-IjB2JR8vylmnd2domnocwxd8eN1sYp-s7HRrotFn3I8mOxDn27RldNdsnd_d4y-Xmer6Vu5fJ8vpi_L0hAhc1kzURHGW8CGUdY6hmuogYNea0c5o5Vw2hKJWY3Xom0phZpXkgKxhrccKjpGj-fefQzfB5uy2oZD7IdJBRXDUoCUYqCezpSJIaVondpHv9PxVwFWJ1GqadRJlBrsjNHDGfbW2n-QCz58zOgRTclh3A</recordid><startdate>20140501</startdate><enddate>20140501</enddate><creator>Parashar, Angshuman</creator><creator>Pellauer, Michael</creator><creator>Adler, Michael</creator><creator>Ahsan, Bushra</creator><creator>Crago, Neal</creator><creator>Lustig, Daniel</creator><creator>Pavlov, Vladimir</creator><creator>Zhai, Antonia</creator><creator>Gambhir, Mohit</creator><creator>Jaleel, Aamer</creator><creator>Allmon, Randy</creator><creator>Rayess, Rachid</creator><creator>Maresh, Stephen</creator><creator>Emer, Joel</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20140501</creationdate><title>Efficient Spatial Processing Element Control via Triggered Instructions</title><author>Parashar, Angshuman ; Pellauer, Michael ; Adler, Michael ; Ahsan, Bushra ; Crago, Neal ; Lustig, Daniel ; Pavlov, Vladimir ; Zhai, Antonia ; Gambhir, Mohit ; Jaleel, Aamer ; Allmon, Randy ; Rayess, Rachid ; Maresh, Stephen ; Emer, Joel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c279t-8475246b10c434bf40818161adaf364357fae290480d7bb3318659312ec6b6153</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Arrays</topic><topic>Computer architecture</topic><topic>Computer programming</topic><topic>Control systems</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>high performance computing</topic><topic>Instruction sets</topic><topic>networking</topic><topic>Parallel processing</topic><topic>processing element</topic><topic>Programming</topic><topic>Radiation detectors</topic><topic>spatial parallelism</topic><topic>triggered instruction</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Parashar, Angshuman</creatorcontrib><creatorcontrib>Pellauer, Michael</creatorcontrib><creatorcontrib>Adler, Michael</creatorcontrib><creatorcontrib>Ahsan, Bushra</creatorcontrib><creatorcontrib>Crago, Neal</creatorcontrib><creatorcontrib>Lustig, Daniel</creatorcontrib><creatorcontrib>Pavlov, Vladimir</creatorcontrib><creatorcontrib>Zhai, Antonia</creatorcontrib><creatorcontrib>Gambhir, Mohit</creatorcontrib><creatorcontrib>Jaleel, Aamer</creatorcontrib><creatorcontrib>Allmon, Randy</creatorcontrib><creatorcontrib>Rayess, Rachid</creatorcontrib><creatorcontrib>Maresh, Stephen</creatorcontrib><creatorcontrib>Emer, Joel</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE MICRO</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Parashar, Angshuman</au><au>Pellauer, Michael</au><au>Adler, Michael</au><au>Ahsan, Bushra</au><au>Crago, Neal</au><au>Lustig, Daniel</au><au>Pavlov, Vladimir</au><au>Zhai, Antonia</au><au>Gambhir, Mohit</au><au>Jaleel, Aamer</au><au>Allmon, Randy</au><au>Rayess, Rachid</au><au>Maresh, Stephen</au><au>Emer, Joel</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Efficient Spatial Processing Element Control via Triggered Instructions</atitle><jtitle>IEEE MICRO</jtitle><stitle>MM</stitle><date>2014-05-01</date><risdate>2014</risdate><volume>34</volume><issue>3</issue><spage>120</spage><epage>137</epage><pages>120-137</pages><issn>0272-1732</issn><eissn>1937-4143</eissn><coden>IEMIDZ</coden><abstract>In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.</abstract><cop>Los Alamitos</cop><pub>IEEE</pub><doi>10.1109/MM.2014.14</doi><tpages>18</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0272-1732 |
ispartof | IEEE MICRO, 2014-05, Vol.34 (3), p.120-137 |
issn | 0272-1732 1937-4143 |
language | eng |
recordid | cdi_crossref_primary_10_1109_MM_2014_14 |
source | IEEE Electronic Library (IEL) |
subjects | Arrays Computer architecture Computer programming Control systems Field programmable gate arrays Hardware high performance computing Instruction sets networking Parallel processing processing element Programming Radiation detectors spatial parallelism triggered instruction |
title | Efficient Spatial Processing Element Control via Triggered Instructions |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T03%3A14%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Efficient%20Spatial%20Processing%20Element%20Control%20via%20Triggered%20Instructions&rft.jtitle=IEEE%20MICRO&rft.au=Parashar,%20Angshuman&rft.date=2014-05-01&rft.volume=34&rft.issue=3&rft.spage=120&rft.epage=137&rft.pages=120-137&rft.issn=0272-1732&rft.eissn=1937-4143&rft.coden=IEMIDZ&rft_id=info:doi/10.1109/MM.2014.14&rft_dat=%3Cproquest_RIE%3E3351625391%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1540971997&rft_id=info:pmid/&rft_ieee_id=6762794&rfr_iscdi=true |