Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts

High-level synthesis from OpenCL has shown significant potential, but current approaches conflict with mainstream OpenCL design methodologies owing to orders-of-magnitude longer field-programmable gate array compilation times and limited support for changing or adding kernels after system compilatio...

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Veröffentlicht in:	IEEE MICRO 2014-01, Vol.34 (1), p.42-53
Hauptverfasser:	Coole, James, Stitt, Greg
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer programming Context awareness Design engineering Field programmable gate arrays Finite impulse response filters FPGA intermediate fabrics Kernels OpenCL Reconfigurable architectures Reconfiguration Runtime Synthesis
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