Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
This work efficiently enables conventional block sizes for very large die-stacked DRAM caches with two innovations: it makes hits faster with compound-access scheduling and misses faster with a MissMap. The combination of these mechanisms enables the new organization to deliver performance comparabl...
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Veröffentlicht in: | IEEE MICRO 2012-05, Vol.32 (3), p.70-78 |
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Hauptverfasser: | , |
Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | This work efficiently enables conventional block sizes for very large die-stacked DRAM caches with two innovations: it makes hits faster with compound-access scheduling and misses faster with a MissMap. The combination of these mechanisms enables the new organization to deliver performance comparable to that of an idealistic DRAM cache that employs an impractically large SRAM-based on-chip tag array. |
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ISSN: | 0272-1732 1937-4143 |
DOI: | 10.1109/MM.2012.25 |