1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off Applications

This letter presents a single-rail two-port static random-access memory (SRAM) designed in 28-nm FD-SOI technology specifically for a synchronous/asynchronous Internet of Things node. This SRAM supports an asynchronous interface communication and a fast transition sleep/active mode. It enables simul...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE solid-state circuits letters 2018-09, Vol.1 (9), p.186-189
Hauptverfasser:	Boumchedda, Reda, Makosiej, Adam, Noel, Jean-Philippe, Giraud, Bastien, Christmann, Jean-Frederic, Miro-Panades, Ivan, Ciampolini, Lorenzo, Royer, Pablo, Mounet, Christopher, Turgis, David, Beigne, Edith
Format:	Artikel
Sprache:	eng
Schlagworte:	Asynchronous static random-access memory (SRAM) Central Processing Unit Clocks Computer architecture Electric potential Energy costs Internet of Things leakage-free read-port Partial discharges Power consumption Random access memory Static random access memory two-port SRAM (TP SRAM) ultralow voltage (ULV) virtual GND Voltage
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!