A Highly Efficient CMOS Envelope Tracking Power Amplifier Using All Bias Node Controls
This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed...
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| Veröffentlicht in: | IEEE microwave and wireless components letters 2015-08, Vol.25 (8), p.517-519 |
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| container_title | IEEE microwave and wireless components letters |
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| creator | Jin, Sangsu Park, Byungjoon Moon, Kyunghoon Kim, Jooseung Kwon, Myeongju Kim, Dongsu Kim, Bumman |
| description | This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 μm CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLRE-UTRA of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR). |
| doi_str_mv | 10.1109/LMWC.2015.2440652 |
| format | Article |
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The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 μm CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLRE-UTRA of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR).</description><identifier>ISSN: 1531-1309</identifier><identifier>ISSN: 2771-957X</identifier><identifier>EISSN: 1558-1764</identifier><identifier>EISSN: 2771-9588</identifier><identifier>DOI: 10.1109/LMWC.2015.2440652</identifier><identifier>CODEN: IMWCBJ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Adaptive bias ; Boards ; Circuit boards ; CMOS ; CMOS integrated circuits ; CMOS technology ; differential ; Electronics industry ; envelope-tracking (ET) ; Gates (circuits) ; Linearity ; linearization ; Logic gates ; LTE ; Modulation ; Peak to average power ratio ; power amplifier (PA) ; Power amplifiers ; Power generation ; Printed circuit boards ; Printed circuits ; Transformers</subject><ispartof>IEEE microwave and wireless components letters, 2015-08, Vol.25 (8), p.517-519</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2015</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c466t-e5d1ffb1d8a8daea3a6d2d7bf1cca0ff3fd5db690ec0a37e01c70fa86b3c00bd3</citedby><cites>FETCH-LOGICAL-c466t-e5d1ffb1d8a8daea3a6d2d7bf1cca0ff3fd5db690ec0a37e01c70fa86b3c00bd3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7121024$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7121024$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jin, Sangsu</creatorcontrib><creatorcontrib>Park, Byungjoon</creatorcontrib><creatorcontrib>Moon, Kyunghoon</creatorcontrib><creatorcontrib>Kim, Jooseung</creatorcontrib><creatorcontrib>Kwon, Myeongju</creatorcontrib><creatorcontrib>Kim, Dongsu</creatorcontrib><creatorcontrib>Kim, Bumman</creatorcontrib><title>A Highly Efficient CMOS Envelope Tracking Power Amplifier Using All Bias Node Controls</title><title>IEEE microwave and wireless components letters</title><addtitle>LMWC</addtitle><description>This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 μm CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLRE-UTRA of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR).</description><subject>Adaptive bias</subject><subject>Boards</subject><subject>Circuit boards</subject><subject>CMOS</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>differential</subject><subject>Electronics industry</subject><subject>envelope-tracking (ET)</subject><subject>Gates (circuits)</subject><subject>Linearity</subject><subject>linearization</subject><subject>Logic gates</subject><subject>LTE</subject><subject>Modulation</subject><subject>Peak to average power ratio</subject><subject>power amplifier (PA)</subject><subject>Power amplifiers</subject><subject>Power generation</subject><subject>Printed circuit boards</subject><subject>Printed circuits</subject><subject>Transformers</subject><issn>1531-1309</issn><issn>2771-957X</issn><issn>1558-1764</issn><issn>2771-9588</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE1P4zAQhi3ESkB3f8CKiyUuXFJm4nz1WKLyIZVlpW3ZY-TYYzC4cbFbUP89iYo4cJpXo-cdjR7GfiOMEWFyMb_7X49TwHycZhkUeXrAjjHPqwTLIjscssAEBUyO2EmMzwCYVRkes4cpv7GPT27HZ8ZYZanb8Pru_h-fdW_k_Jr4Ikj1YrtH_te_U-DT1dpZY_u0jMN26hy_tDLyP14Tr323Cd7Fn-yHkS7Sr885Ysur2aK-Seb317f1dJ6orCg2CeUajWlRV7LSkqSQhU512RpUSoIxwuhct8UESIEUJQGqEoysilYogFaLETvf310H_7qluGlWNipyTnbkt7HBUgBkZQ7Yo2ff0Ge_DV3_XU9BWlYp9pJGDPeUCj7GQKZZB7uSYdcgNIPpZjDdDKabT9N953TfsUT0xZeYIqSZ-ABqVHmy</recordid><startdate>20150801</startdate><enddate>20150801</enddate><creator>Jin, Sangsu</creator><creator>Park, Byungjoon</creator><creator>Moon, Kyunghoon</creator><creator>Kim, Jooseung</creator><creator>Kwon, Myeongju</creator><creator>Kim, Dongsu</creator><creator>Kim, Bumman</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20150801</creationdate><title>A Highly Efficient CMOS Envelope Tracking Power Amplifier Using All Bias Node Controls</title><author>Jin, Sangsu ; Park, Byungjoon ; Moon, Kyunghoon ; Kim, Jooseung ; Kwon, Myeongju ; Kim, Dongsu ; Kim, Bumman</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c466t-e5d1ffb1d8a8daea3a6d2d7bf1cca0ff3fd5db690ec0a37e01c70fa86b3c00bd3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2015</creationdate><topic>Adaptive bias</topic><topic>Boards</topic><topic>Circuit boards</topic><topic>CMOS</topic><topic>CMOS integrated circuits</topic><topic>CMOS technology</topic><topic>differential</topic><topic>Electronics industry</topic><topic>envelope-tracking (ET)</topic><topic>Gates (circuits)</topic><topic>Linearity</topic><topic>linearization</topic><topic>Logic gates</topic><topic>LTE</topic><topic>Modulation</topic><topic>Peak to average power ratio</topic><topic>power amplifier (PA)</topic><topic>Power amplifiers</topic><topic>Power generation</topic><topic>Printed circuit boards</topic><topic>Printed circuits</topic><topic>Transformers</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jin, Sangsu</creatorcontrib><creatorcontrib>Park, Byungjoon</creatorcontrib><creatorcontrib>Moon, Kyunghoon</creatorcontrib><creatorcontrib>Kim, Jooseung</creatorcontrib><creatorcontrib>Kwon, Myeongju</creatorcontrib><creatorcontrib>Kim, Dongsu</creatorcontrib><creatorcontrib>Kim, Bumman</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE microwave and wireless components letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jin, Sangsu</au><au>Park, Byungjoon</au><au>Moon, Kyunghoon</au><au>Kim, Jooseung</au><au>Kwon, Myeongju</au><au>Kim, Dongsu</au><au>Kim, Bumman</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Highly Efficient CMOS Envelope Tracking Power Amplifier Using All Bias Node Controls</atitle><jtitle>IEEE microwave and wireless components letters</jtitle><stitle>LMWC</stitle><date>2015-08-01</date><risdate>2015</risdate><volume>25</volume><issue>8</issue><spage>517</spage><epage>519</epage><pages>517-519</pages><issn>1531-1309</issn><issn>2771-957X</issn><eissn>1558-1764</eissn><eissn>2771-9588</eissn><coden>IMWCBJ</coden><abstract>This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 μm CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLRE-UTRA of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR).</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LMWC.2015.2440652</doi><tpages>3</tpages></addata></record> |
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| subjects | Adaptive bias Boards Circuit boards CMOS CMOS integrated circuits CMOS technology differential Electronics industry envelope-tracking (ET) Gates (circuits) Linearity linearization Logic gates LTE Modulation Peak to average power ratio power amplifier (PA) Power amplifiers Power generation Printed circuit boards Printed circuits Transformers |
| title | A Highly Efficient CMOS Envelope Tracking Power Amplifier Using All Bias Node Controls |
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