A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs

Integrating more functionality in a smaller form factor with higher performance and lower power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next...

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Veröffentlicht in:	IEEE embedded systems letters 2011-09, Vol.3 (3), p.97-100
Hauptverfasser:	Siozios, K., Soudris, D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Computer aided design Computer-aided design (CAD) tool Delay Design automation Electronics Field programmable gate arrays field-programmable gate array (FPGA) Integrated circuit interconnections Integrated circuit modeling Partitioning partitioning algorithm Partitioning algorithms Power consumption Projectiles Routing Semiconductors Three dimensional three-dimensional (3-D) architectures
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