A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs
Integrating more functionality in a smaller form factor with higher performance and lower power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next...
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| Veröffentlicht in: | IEEE embedded systems letters 2011-09, Vol.3 (3), p.97-100 |
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| container_title | IEEE embedded systems letters |
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| creator | Siozios, K. Soudris, D. |
| description | Integrating more functionality in a smaller form factor with higher performance and lower power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. This letter introduces a TSV-aware partitioning algorithm that enables higher performance for application implementation onto 3-D field-programmable gate arrays (FPGAs). Unlike other algorithms that minimize the number of connections among layers, our solution leads to a more efficient utilization of the available (fabricated) interlayer connectivity. Experimental results show average reductions in delay and power consumption, as compared to similar 3-D computer-aided design (CAD) tools, about 28% and 26%, respectively. |
| doi_str_mv | 10.1109/LES.2011.2161571 |
| format | Article |
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| identifier | ISSN: 1943-0663 |
| ispartof | IEEE embedded systems letters, 2011-09, Vol.3 (3), p.97-100 |
| issn | 1943-0663 1943-0671 |
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| source | IEEE/IET Electronic Library (IEL) |
| subjects | Algorithms Computer aided design Computer-aided design (CAD) tool Delay Design automation Electronics Field programmable gate arrays field-programmable gate array (FPGA) Integrated circuit interconnections Integrated circuit modeling Partitioning partitioning algorithm Partitioning algorithms Power consumption Projectiles Routing Semiconductors Three dimensional three-dimensional (3-D) architectures |
| title | A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs |
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