Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors
This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In add...
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| Veröffentlicht in: | IEEE electron device letters 2019-12, Vol.40 (12), p.1941-1944 |
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| container_end_page | 1944 |
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| container_issue | 12 |
| container_start_page | 1941 |
| container_title | IEEE electron device letters |
| container_volume | 40 |
| creator | Chen, Hong-Chih Tsao, Yu-Ching Chu, An-Kuo Huang, Hui-Chun Lai, Wei-Chih Chen, Guan-Fu Huang, Shin-Ping Chang, Ting-Chang Chen, Po-Hsun Chen, Jian-Jie Kuo, Chuan-Wei Zhou, Kuan-Ju Hung, Yang-Hao |
| description | This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field. |
| doi_str_mv | 10.1109/LED.2019.2949243 |
| format | Article |
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The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2019.2949243</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bias ; Degradation ; Dielectrics ; Electric field ; Electric fields ; Electron traps ; illumination ; Insulating layers ; Insulation ; Logic gates ; Organic thin film transistors ; organic thin-film transistors (OTFT) ; reliability ; Semiconductor devices ; Stress ; Thin film transistors ; Transistors</subject><ispartof>IEEE electron device letters, 2019-12, Vol.40 (12), p.1941-1944</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-807d21154ce51cc8b7a4d22c332d8b0107cd6c691db37bb285bc691ade54964c3</citedby><cites>FETCH-LOGICAL-c291t-807d21154ce51cc8b7a4d22c332d8b0107cd6c691db37bb285bc691ade54964c3</cites><orcidid>0000-0002-5301-6693 ; 0000-0003-2703-8845 ; 0000-0003-4864-1010 ; 0000-0001-5223-793X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8880614$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27915,27916,54749</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8880614$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chen, Hong-Chih</creatorcontrib><creatorcontrib>Tsao, Yu-Ching</creatorcontrib><creatorcontrib>Chu, An-Kuo</creatorcontrib><creatorcontrib>Huang, Hui-Chun</creatorcontrib><creatorcontrib>Lai, Wei-Chih</creatorcontrib><creatorcontrib>Chen, Guan-Fu</creatorcontrib><creatorcontrib>Huang, Shin-Ping</creatorcontrib><creatorcontrib>Chang, Ting-Chang</creatorcontrib><creatorcontrib>Chen, Po-Hsun</creatorcontrib><creatorcontrib>Chen, Jian-Jie</creatorcontrib><creatorcontrib>Kuo, Chuan-Wei</creatorcontrib><creatorcontrib>Zhou, Kuan-Ju</creatorcontrib><creatorcontrib>Hung, Yang-Hao</creatorcontrib><title>Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.</description><subject>Bias</subject><subject>Degradation</subject><subject>Dielectrics</subject><subject>Electric field</subject><subject>Electric fields</subject><subject>Electron traps</subject><subject>illumination</subject><subject>Insulating layers</subject><subject>Insulation</subject><subject>Logic gates</subject><subject>Organic thin film transistors</subject><subject>organic thin-film transistors (OTFT)</subject><subject>reliability</subject><subject>Semiconductor devices</subject><subject>Stress</subject><subject>Thin film transistors</subject><subject>Transistors</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1LxDAQhoMouK7eBS8Bz62ZJG3To-6nsLAH6zmkaapZtk1N0oP_3i67eBoGnnde5kHoEUgKQMqX3WqZUgJlSkteUs6u0AyyTCQky9k1mpGCQ8KA5LfoLoQDIcB5wWfoc-18p6J1PXYt3o7dgFdta3TEy9Hg6HDlhmSjosFvVgX8Eb0JAdse7_2X6q3G1bftk7U9drjyqg82ROfDPbpp1TGYh8ucTz2rarFNdvvN--J1l2haQkwEKRoKkHFtMtBa1IXiDaWaMdqImgApdJPrvISmZkVdU5HVp001JuNlzjWbo-fz3cG7n9GEKA9u9P1UKSmjEz89SSaKnCntXQjetHLwtlP-VwKRJ3lykidP8uRF3hR5OkesMeYfF0KQHDj7Axu8aSs</recordid><startdate>20191201</startdate><enddate>20191201</enddate><creator>Chen, Hong-Chih</creator><creator>Tsao, Yu-Ching</creator><creator>Chu, An-Kuo</creator><creator>Huang, Hui-Chun</creator><creator>Lai, Wei-Chih</creator><creator>Chen, Guan-Fu</creator><creator>Huang, Shin-Ping</creator><creator>Chang, Ting-Chang</creator><creator>Chen, Po-Hsun</creator><creator>Chen, Jian-Jie</creator><creator>Kuo, Chuan-Wei</creator><creator>Zhou, Kuan-Ju</creator><creator>Hung, Yang-Hao</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LED.2019.2949243</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-5301-6693</orcidid><orcidid>https://orcid.org/0000-0003-2703-8845</orcidid><orcidid>https://orcid.org/0000-0003-4864-1010</orcidid><orcidid>https://orcid.org/0000-0001-5223-793X</orcidid></addata></record> |
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| subjects | Bias Degradation Dielectrics Electric field Electric fields Electron traps illumination Insulating layers Insulation Logic gates Organic thin film transistors organic thin-film transistors (OTFT) reliability Semiconductor devices Stress Thin film transistors Transistors |
| title | Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors |
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