Investigation of Hump Effect of Amorphous In-Ga-Zn-O Thin-Film Transistor Using Scanning Capacitance Microscopy
We investigated the hump effect, which is induced by positive gate-bias stress, of an amorphous In-Ga-Zn-O thin-film transistor with the self-aligned top-gate structure. By applying scanning capacitance microscopy to the transistor with the hump effect, we directly detected a partial increase of car...
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Veröffentlicht in: | IEEE electron device letters 2019-08, Vol.40 (8), p.1273-1276 |
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creator | Kuwahara, Yuya Takechi, Kazushige Tanaka, Jun Tanabe, Hiroshi |
description | We investigated the hump effect, which is induced by positive gate-bias stress, of an amorphous In-Ga-Zn-O thin-film transistor with the self-aligned top-gate structure. By applying scanning capacitance microscopy to the transistor with the hump effect, we directly detected a partial increase of carrier density at the channel edges in the channel width direction. The width of the high-carrier-density regions was approximately {1}\,{\mu \text {m}} at each side edge, which is consistent with the estimation by electrical measurements. Such high-carrier regions at the channel edges can act as parasitic transistors with a more negative threshold voltage, generating the hump in the transfer characteristics. Our results support the idea that the hump effect is derived from the parasitic transistors at the channel edges directly and show that the scanning capacitance microscopy provides complementary information to the electrical measurements and is an effective tool to evaluate the hump effect. |
doi_str_mv | 10.1109/LED.2019.2924484 |
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By applying scanning capacitance microscopy to the transistor with the hump effect, we directly detected a partial increase of carrier density at the channel edges in the channel width direction. The width of the high-carrier-density regions was approximately <inline-formula> <tex-math notation="LaTeX">{1}\,{\mu \text {m}} </tex-math></inline-formula> at each side edge, which is consistent with the estimation by electrical measurements. Such high-carrier regions at the channel edges can act as parasitic transistors with a more negative threshold voltage, generating the hump in the transfer characteristics. Our results support the idea that the hump effect is derived from the parasitic transistors at the channel edges directly and show that the scanning capacitance microscopy provides complementary information to the electrical measurements and is an effective tool to evaluate the hump effect.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2019.2924484</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>amorphous IGZO ; Capacitance ; Carrier density ; Electrical measurement ; Hump effect ; Indium gallium zinc oxide ; Insulators ; Logic gates ; Microscopy ; parasitic transistor ; positive bias stress ; scanning capacitance microscopy ; Self alignment ; Semiconductor device measurement ; Semiconductor devices ; Stress ; thin film transistor ; Thin film transistors ; Thin films ; Threshold voltage ; Transistors</subject><ispartof>IEEE electron device letters, 2019-08, Vol.40 (8), p.1273-1276</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-8c9bc2962be391b1c8753ec0aa530badc5fdc9515d84d69838ab3c59af702a9b3</citedby><cites>FETCH-LOGICAL-c291t-8c9bc2962be391b1c8753ec0aa530badc5fdc9515d84d69838ab3c59af702a9b3</cites><orcidid>0000-0001-6071-2091 ; 0000-0002-7632-1789 ; 0000-0001-5312-2536 ; 0000-0001-7084-8371</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8744301$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8744301$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kuwahara, Yuya</creatorcontrib><creatorcontrib>Takechi, Kazushige</creatorcontrib><creatorcontrib>Tanaka, Jun</creatorcontrib><creatorcontrib>Tanabe, Hiroshi</creatorcontrib><title>Investigation of Hump Effect of Amorphous In-Ga-Zn-O Thin-Film Transistor Using Scanning Capacitance Microscopy</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>We investigated the hump effect, which is induced by positive gate-bias stress, of an amorphous In-Ga-Zn-O thin-film transistor with the self-aligned top-gate structure. By applying scanning capacitance microscopy to the transistor with the hump effect, we directly detected a partial increase of carrier density at the channel edges in the channel width direction. The width of the high-carrier-density regions was approximately <inline-formula> <tex-math notation="LaTeX">{1}\,{\mu \text {m}} </tex-math></inline-formula> at each side edge, which is consistent with the estimation by electrical measurements. Such high-carrier regions at the channel edges can act as parasitic transistors with a more negative threshold voltage, generating the hump in the transfer characteristics. Our results support the idea that the hump effect is derived from the parasitic transistors at the channel edges directly and show that the scanning capacitance microscopy provides complementary information to the electrical measurements and is an effective tool to evaluate the hump effect.</description><subject>amorphous IGZO</subject><subject>Capacitance</subject><subject>Carrier density</subject><subject>Electrical measurement</subject><subject>Hump effect</subject><subject>Indium gallium zinc oxide</subject><subject>Insulators</subject><subject>Logic gates</subject><subject>Microscopy</subject><subject>parasitic transistor</subject><subject>positive bias stress</subject><subject>scanning capacitance microscopy</subject><subject>Self alignment</subject><subject>Semiconductor device measurement</subject><subject>Semiconductor devices</subject><subject>Stress</subject><subject>thin film transistor</subject><subject>Thin film transistors</subject><subject>Thin films</subject><subject>Threshold voltage</subject><subject>Transistors</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1LwzAYxoMoOKd3wUvAc2bSJG1zHHNfMNnB7eIlpGm6ZaxJTVph_70tE0_v88LzvB8_AJ4JnhCCxdtm_j5JMBGTRCSM5ewGjAjnOcI8pbdghDNGECU4vQcPMZ4wJoxlbAT82v2Y2NqDaq130Fdw1dUNnFeV0e3QTmsfmqPvIlw7tFToy6Et3B2tQwt7ruEuKBdtbH2A-2jdAX5q5dwgZqpR2rbKaQM_rA4-at9cHsFdpc7RPP3VMdgv5rvZCm22y_VsukE6EaRFuRZFr9KkMFSQgug849RorBSnuFCl5lWpBSe8zFmZipzmqqCaC1VlOFGioGPwep3bBP_d9R_Kk--C61fKJEkZo0xw1rvw1TWcF4OpZBNsrcJFEiwHrLLHKges8g9rH3m5Rqwx5t-eZ_1ITOgvSjZz5Q</recordid><startdate>20190801</startdate><enddate>20190801</enddate><creator>Kuwahara, Yuya</creator><creator>Takechi, Kazushige</creator><creator>Tanaka, Jun</creator><creator>Tanabe, Hiroshi</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-6071-2091</orcidid><orcidid>https://orcid.org/0000-0002-7632-1789</orcidid><orcidid>https://orcid.org/0000-0001-5312-2536</orcidid><orcidid>https://orcid.org/0000-0001-7084-8371</orcidid></search><sort><creationdate>20190801</creationdate><title>Investigation of Hump Effect of Amorphous In-Ga-Zn-O Thin-Film Transistor Using Scanning Capacitance Microscopy</title><author>Kuwahara, Yuya ; Takechi, Kazushige ; Tanaka, Jun ; Tanabe, Hiroshi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-8c9bc2962be391b1c8753ec0aa530badc5fdc9515d84d69838ab3c59af702a9b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>amorphous IGZO</topic><topic>Capacitance</topic><topic>Carrier density</topic><topic>Electrical measurement</topic><topic>Hump effect</topic><topic>Indium gallium zinc oxide</topic><topic>Insulators</topic><topic>Logic gates</topic><topic>Microscopy</topic><topic>parasitic transistor</topic><topic>positive bias stress</topic><topic>scanning capacitance microscopy</topic><topic>Self alignment</topic><topic>Semiconductor device measurement</topic><topic>Semiconductor devices</topic><topic>Stress</topic><topic>thin film transistor</topic><topic>Thin film transistors</topic><topic>Thin films</topic><topic>Threshold voltage</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kuwahara, Yuya</creatorcontrib><creatorcontrib>Takechi, Kazushige</creatorcontrib><creatorcontrib>Tanaka, Jun</creatorcontrib><creatorcontrib>Tanabe, Hiroshi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kuwahara, Yuya</au><au>Takechi, Kazushige</au><au>Tanaka, Jun</au><au>Tanabe, Hiroshi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Investigation of Hump Effect of Amorphous In-Ga-Zn-O Thin-Film Transistor Using Scanning Capacitance Microscopy</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2019-08-01</date><risdate>2019</risdate><volume>40</volume><issue>8</issue><spage>1273</spage><epage>1276</epage><pages>1273-1276</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>We investigated the hump effect, which is induced by positive gate-bias stress, of an amorphous In-Ga-Zn-O thin-film transistor with the self-aligned top-gate structure. By applying scanning capacitance microscopy to the transistor with the hump effect, we directly detected a partial increase of carrier density at the channel edges in the channel width direction. The width of the high-carrier-density regions was approximately <inline-formula> <tex-math notation="LaTeX">{1}\,{\mu \text {m}} </tex-math></inline-formula> at each side edge, which is consistent with the estimation by electrical measurements. Such high-carrier regions at the channel edges can act as parasitic transistors with a more negative threshold voltage, generating the hump in the transfer characteristics. Our results support the idea that the hump effect is derived from the parasitic transistors at the channel edges directly and show that the scanning capacitance microscopy provides complementary information to the electrical measurements and is an effective tool to evaluate the hump effect.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LED.2019.2924484</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0001-6071-2091</orcidid><orcidid>https://orcid.org/0000-0002-7632-1789</orcidid><orcidid>https://orcid.org/0000-0001-5312-2536</orcidid><orcidid>https://orcid.org/0000-0001-7084-8371</orcidid></addata></record> |
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subjects | amorphous IGZO Capacitance Carrier density Electrical measurement Hump effect Indium gallium zinc oxide Insulators Logic gates Microscopy parasitic transistor positive bias stress scanning capacitance microscopy Self alignment Semiconductor device measurement Semiconductor devices Stress thin film transistor Thin film transistors Thin films Threshold voltage Transistors |
title | Investigation of Hump Effect of Amorphous In-Ga-Zn-O Thin-Film Transistor Using Scanning Capacitance Microscopy |
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