Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity
In this letter, we present complementary tunneling field-effect transistors (CTFETs) based on strained Si with gate all around nanowire structures on a single chip. The main focus is to suppress the ambipolar behavior of the TFETs with a gate-drain underlap. Detailed device characterization and demo...
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| Veröffentlicht in: | IEEE electron device letters 2016-08, Vol.37 (8), p.950-953 |
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| container_title | IEEE electron device letters |
| container_volume | 37 |
| creator | Luong, G. V. Narimani, K. Tiedemann, A. T. Bernardy, P. Trellenkamp, S. Zhao, Q. T. Mantl, S. |
| description | In this letter, we present complementary tunneling field-effect transistors (CTFETs) based on strained Si with gate all around nanowire structures on a single chip. The main focus is to suppress the ambipolar behavior of the TFETs with a gate-drain underlap. Detailed device characterization and demonstration of a CTFET inverter show that the ambipolar current is successfully eliminated for both pand n-devices. The CTFET inverter transfer characteristics indicate maximum separation of the high/low level with a sharp transition (high voltage gain) at a Vdd down to 0.4 V. In addition, high noise margin levels of 40% of the applied Vdd are obtained. |
| doi_str_mv | 10.1109/LED.2016.2582041 |
| format | Article |
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In addition, high noise margin levels of 40% of the applied Vdd are obtained.</description><subject>ambipolar behavior</subject><subject>CTFET</subject><subject>Devices</subject><subject>Gain</subject><subject>Gates</subject><subject>High voltages</subject><subject>inverter</subject><subject>Inverters</subject><subject>Junctions</subject><subject>Logic gates</subject><subject>Low level</subject><subject>Nanowires</subject><subject>Silicides</subject><subject>Silicon</subject><subject>Silicon nanowire</subject><subject>TFETs</subject><subject>Tunneling</subject><subject>tunneling FET</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkD1LA0EQQBdRMEZ7webAxubi7PdtGWKMQlAkEctjc5nDDffl7kXJv3dDgoXVwPDeMDxCrimMKAVzP58-jBhQNWIyYyDoCRlQKbMUpOKnZABa0JRTUOfkIoQNABVCiwF5m7R1V2GNTW_9Lln03roG18nCJbPxOHmxTfvjPCbLx-kyeW6-0ffokw_XfyaLbdd5DCHS43rluray3vW7S3JW2irg1XEOyXt0J0_p_HX2PBnP04Ib0acSbCkMlCqTrKSM2lWBtBQrAYqvjNWlXrO1LDIhC62ZNMjW2sQNWlkYwzgfkrvD3c63X1sMfV67UGBV2QbbbchpxqWCTCoZ0dt_6Kbd-iZ-FylQIgOa6UjBgSp8G4LHMu-8q2OVnEK-b5zHxvm-cX5sHJWbg-IQ8Q_XwnDFgf8CKiZ2Hg</recordid><startdate>201608</startdate><enddate>201608</enddate><creator>Luong, G. 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T.</creatorcontrib><creatorcontrib>Bernardy, P.</creatorcontrib><creatorcontrib>Trellenkamp, S.</creatorcontrib><creatorcontrib>Zhao, Q. T.</creatorcontrib><creatorcontrib>Mantl, S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Luong, G. V.</au><au>Narimani, K.</au><au>Tiedemann, A. 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| subjects | ambipolar behavior CTFET Devices Gain Gates High voltages inverter Inverters Junctions Logic gates Low level Nanowires Silicides Silicon Silicon nanowire TFETs Tunneling tunneling FET |
| title | Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity |
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