Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates
Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owi...
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| Veröffentlicht in: | IEEE electron device letters 2015-08, Vol.36 (8), p.796-798 |
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| container_title | IEEE electron device letters |
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| creator | Rong-Jhe Lyu Horng-Chih Lin Tiao-Yuan Huang |
| description | Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance. |
| doi_str_mv | 10.1109/LED.2015.2445772 |
| format | Article |
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Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2015.2445772</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>IEEE</publisher><subject>film profile engineering (FPE) ; II-VI semiconductor materials ; Logic gates ; Metal oxides ; Thin film transistors ; thin-film transistor ; Tin ; Wires ; Zinc oxide ; ZnO</subject><ispartof>IEEE electron device letters, 2015-08, Vol.36 (8), p.796-798</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c263t-3e726195eb9597ca169b1d3d84b7c5523f049f13f5c465447a55fc4572dd87503</citedby><cites>FETCH-LOGICAL-c263t-3e726195eb9597ca169b1d3d84b7c5523f049f13f5c465447a55fc4572dd87503</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7124440$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,778,782,794,27907,27908,54741</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7124440$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Rong-Jhe Lyu</creatorcontrib><creatorcontrib>Horng-Chih Lin</creatorcontrib><creatorcontrib>Tiao-Yuan Huang</creatorcontrib><title>Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.</description><subject>film profile engineering (FPE)</subject><subject>II-VI semiconductor materials</subject><subject>Logic gates</subject><subject>Metal oxides</subject><subject>Thin film transistors</subject><subject>thin-film transistor</subject><subject>Tin</subject><subject>Wires</subject><subject>Zinc oxide</subject><subject>ZnO</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1LAzEURYMoWKt7wU3-QGoySSadpfYbCi1SEdwMaebFRmcmJYkL9_5wZ2hx9Rb33AvvIHTP6IgxWjyuZ9NRRpkcZUJIpbILNGBSjgmVOb9EA6oEI5zR_BrdxPhJKRNCiQH6XTVHbRL2Fr9AdNW3rvFSh6rR8Qu_uQAR-xanA-AtBOtDo1sDPT13dUO2wVtXA5m1H64FCFDh93aDdwfXkh7Au6Db6GLyIXZr6YCnLpoACfCzT8k3eKETxFt0ZXUd4e58h-h1PttNlmS9WawmT2tispwnwkFlOSsk7AtZKKNZXuxZxaux2CsjZcYtFYVl3Eojctn9p6W0prORVdVYScqHiJ52TfAxBrDlMbhGh5-S0bK3WHYWy95iebbYVR5OFQcA_7hiXS4o_wNJvG5j</recordid><startdate>201508</startdate><enddate>201508</enddate><creator>Rong-Jhe Lyu</creator><creator>Horng-Chih Lin</creator><creator>Tiao-Yuan Huang</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201508</creationdate><title>Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates</title><author>Rong-Jhe Lyu ; Horng-Chih Lin ; Tiao-Yuan Huang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c263t-3e726195eb9597ca169b1d3d84b7c5523f049f13f5c465447a55fc4572dd87503</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2015</creationdate><topic>film profile engineering (FPE)</topic><topic>II-VI semiconductor materials</topic><topic>Logic gates</topic><topic>Metal oxides</topic><topic>Thin film transistors</topic><topic>thin-film transistor</topic><topic>Tin</topic><topic>Wires</topic><topic>Zinc oxide</topic><topic>ZnO</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Rong-Jhe Lyu</creatorcontrib><creatorcontrib>Horng-Chih Lin</creatorcontrib><creatorcontrib>Tiao-Yuan Huang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rong-Jhe Lyu</au><au>Horng-Chih Lin</au><au>Tiao-Yuan Huang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2015-08</date><risdate>2015</risdate><volume>36</volume><issue>8</issue><spage>796</spage><epage>798</epage><pages>796-798</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.</abstract><pub>IEEE</pub><doi>10.1109/LED.2015.2445772</doi><tpages>3</tpages></addata></record> |
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| subjects | film profile engineering (FPE) II-VI semiconductor materials Logic gates Metal oxides Thin film transistors thin-film transistor Tin Wires Zinc oxide ZnO |
| title | Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates |
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