Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory
We compare three dominant mechanisms in two generations of NAND Flash main chips for mass production. In addition, we analyze the charge loss behaviors of each mechanism according to cycling times. As a result, we confirm that as NAND Flash memory is scaled down, the portion of the interface trap re...
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| Veröffentlicht in: | IEEE electron device letters 2013-09, Vol.34 (9), p.1139-1141 |
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| container_end_page | 1141 |
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| container_issue | 9 |
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| container_title | IEEE electron device letters |
| container_volume | 34 |
| creator | Kang, Duckseoung Lee, Kyunghwan Seo, Seongjun Kim, Shinhyung Lee, Ji-Seok Bae, Dong-Seok Li, Dong Hua Hwang, Yuchul Shin, Hyungcheol |
| description | We compare three dominant mechanisms in two generations of NAND Flash main chips for mass production. In addition, we analyze the charge loss behaviors of each mechanism according to cycling times. As a result, we confirm that as NAND Flash memory is scaled down, the portion of the interface trap recovery mechanism increases and the sensitivity of cycling times also increases. In the detrapping mechanism, while the charge loss of next generation is more sensitive on cycling times, the amplitude of the charge loss is larger in the current generation. Simultaneously, when the program operation is performed, the number of electrons injected into the floating gate decreases as the physical size of the device decreases. It lowers the portion of the trap-assisted tunneling mechanism and its trend is also accelerated actively as the cycling times increase. |
| doi_str_mv | 10.1109/LED.2013.2271351 |
| format | Article |
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In addition, we analyze the charge loss behaviors of each mechanism according to cycling times. As a result, we confirm that as NAND Flash memory is scaled down, the portion of the interface trap recovery mechanism increases and the sensitivity of cycling times also increases. In the detrapping mechanism, while the charge loss of next generation is more sensitive on cycling times, the amplitude of the charge loss is larger in the current generation. Simultaneously, when the program operation is performed, the number of electrons injected into the floating gate decreases as the physical size of the device decreases. It lowers the portion of the trap-assisted tunneling mechanism and its trend is also accelerated actively as the cycling times increase.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2013.2271351</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Activation energy ({E}_{a}) ; Applied sciences ; Ash ; Circuit properties ; cycling dependence ; Design. Technologies. Operation analysis. Testing ; detrapping mechanism ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electron traps ; Electronic circuits ; Electronics ; Exact sciences and technology ; failure mechanism ; Flash memories ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; interface trap recovery ; NAND Flash memory ; Next generation networking ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; trap-assisted tunneling (TAT) ; Tunneling</subject><ispartof>IEEE electron device letters, 2013-09, Vol.34 (9), p.1139-1141</ispartof><rights>2014 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-4d61dc0451bcf1260f6ed68e9e7618a9494a3eb5f36e9e278d5609395f3ddf8f3</citedby><cites>FETCH-LOGICAL-c293t-4d61dc0451bcf1260f6ed68e9e7618a9494a3eb5f36e9e278d5609395f3ddf8f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6557027$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54737</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6557027$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=27734985$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kang, Duckseoung</creatorcontrib><creatorcontrib>Lee, Kyunghwan</creatorcontrib><creatorcontrib>Seo, Seongjun</creatorcontrib><creatorcontrib>Kim, Shinhyung</creatorcontrib><creatorcontrib>Lee, Ji-Seok</creatorcontrib><creatorcontrib>Bae, Dong-Seok</creatorcontrib><creatorcontrib>Li, Dong Hua</creatorcontrib><creatorcontrib>Hwang, Yuchul</creatorcontrib><creatorcontrib>Shin, Hyungcheol</creatorcontrib><title>Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>We compare three dominant mechanisms in two generations of NAND Flash main chips for mass production. In addition, we analyze the charge loss behaviors of each mechanism according to cycling times. As a result, we confirm that as NAND Flash memory is scaled down, the portion of the interface trap recovery mechanism increases and the sensitivity of cycling times also increases. In the detrapping mechanism, while the charge loss of next generation is more sensitive on cycling times, the amplitude of the charge loss is larger in the current generation. Simultaneously, when the program operation is performed, the number of electrons injected into the floating gate decreases as the physical size of the device decreases. It lowers the portion of the trap-assisted tunneling mechanism and its trend is also accelerated actively as the cycling times increase.</description><subject>Activation energy ({E}_{a})</subject><subject>Applied sciences</subject><subject>Ash</subject><subject>Circuit properties</subject><subject>cycling dependence</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>detrapping mechanism</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electron traps</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>failure mechanism</subject><subject>Flash memories</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>interface trap recovery</subject><subject>NAND Flash memory</subject><subject>Next generation networking</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>trap-assisted tunneling (TAT)</subject><subject>Tunneling</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtLAzEURoMoWKt7wU02Lqfmncmy9KVQK_gAd0Oa3NCRaaYks7D_3qktXV049_sul4PQPSUjSol5Ws6mI0YoHzGmKZf0Ag2olGVBpOKXaEC0oAWnRF2jm5x_CKFCaDFA3wuIkGxXtxFPYQfRQ3SA24DfoYP4zycbm6zrINW5q13GdcSz3y7BFpo9_nC2AY9X49UUzxubN_gVtm3a36KrYJsMd6c5RF_z2efkuVi-LV4m42XhmOFdIbyi3hEh6doFyhQJCrwqwYBWtLRGGGE5rGXgqmdMl14qYrjpgfehDHyIyPGuS23OCUK1S_XWpn1FSXUwU_VmqoOZ6mSmrzweKzub--9DstHV-dxjWnNhStnnHo65GgDOayWlJkzzP3QrbEQ</recordid><startdate>20130901</startdate><enddate>20130901</enddate><creator>Kang, Duckseoung</creator><creator>Lee, Kyunghwan</creator><creator>Seo, Seongjun</creator><creator>Kim, Shinhyung</creator><creator>Lee, Ji-Seok</creator><creator>Bae, Dong-Seok</creator><creator>Li, Dong Hua</creator><creator>Hwang, Yuchul</creator><creator>Shin, Hyungcheol</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20130901</creationdate><title>Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory</title><author>Kang, Duckseoung ; Lee, Kyunghwan ; Seo, Seongjun ; Kim, Shinhyung ; Lee, Ji-Seok ; Bae, Dong-Seok ; Li, Dong Hua ; Hwang, Yuchul ; Shin, Hyungcheol</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-4d61dc0451bcf1260f6ed68e9e7618a9494a3eb5f36e9e278d5609395f3ddf8f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Activation energy ({E}_{a})</topic><topic>Applied sciences</topic><topic>Ash</topic><topic>Circuit properties</topic><topic>cycling dependence</topic><topic>Design. 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Solid state devices</topic><topic>trap-assisted tunneling (TAT)</topic><topic>Tunneling</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kang, Duckseoung</creatorcontrib><creatorcontrib>Lee, Kyunghwan</creatorcontrib><creatorcontrib>Seo, Seongjun</creatorcontrib><creatorcontrib>Kim, Shinhyung</creatorcontrib><creatorcontrib>Lee, Ji-Seok</creatorcontrib><creatorcontrib>Bae, Dong-Seok</creatorcontrib><creatorcontrib>Li, Dong Hua</creatorcontrib><creatorcontrib>Hwang, Yuchul</creatorcontrib><creatorcontrib>Shin, Hyungcheol</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kang, Duckseoung</au><au>Lee, Kyunghwan</au><au>Seo, Seongjun</au><au>Kim, Shinhyung</au><au>Lee, Ji-Seok</au><au>Bae, Dong-Seok</au><au>Li, Dong Hua</au><au>Hwang, Yuchul</au><au>Shin, Hyungcheol</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2013-09-01</date><risdate>2013</risdate><volume>34</volume><issue>9</issue><spage>1139</spage><epage>1141</epage><pages>1139-1141</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>We compare three dominant mechanisms in two generations of NAND Flash main chips for mass production. In addition, we analyze the charge loss behaviors of each mechanism according to cycling times. As a result, we confirm that as NAND Flash memory is scaled down, the portion of the interface trap recovery mechanism increases and the sensitivity of cycling times also increases. In the detrapping mechanism, while the charge loss of next generation is more sensitive on cycling times, the amplitude of the charge loss is larger in the current generation. Simultaneously, when the program operation is performed, the number of electrons injected into the floating gate decreases as the physical size of the device decreases. It lowers the portion of the trap-assisted tunneling mechanism and its trend is also accelerated actively as the cycling times increase.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2013.2271351</doi><tpages>3</tpages></addata></record> |
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| subjects | Activation energy ({E}_{a}) Applied sciences Ash Circuit properties cycling dependence Design. Technologies. Operation analysis. Testing detrapping mechanism Digital circuits Electric, optical and optoelectronic circuits Electron traps Electronic circuits Electronics Exact sciences and technology failure mechanism Flash memories Integrated circuits Integrated circuits by function (including memories and processors) interface trap recovery NAND Flash memory Next generation networking Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices trap-assisted tunneling (TAT) Tunneling |
| title | Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory |
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