Rethinking Massive MIMO Detection: A Memristor Approach
Efficient implementation of massive multiple-input-multiple-output (MIMO) detection is essential for practical systems. To reduce the computational complexity and high power consumption in MIMO detection process, we propose a memristor-based analog circuit for massive MIMO detection in this letter....
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| Veröffentlicht in: | IEEE communications letters 2023-12, Vol.27 (12), p.3350-3354 |
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| container_issue | 12 |
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| container_title | IEEE communications letters |
| container_volume | 27 |
| creator | Fang, Yiming Chen, Li You, Changsheng Yin, Huarui |
| description | Efficient implementation of massive multiple-input-multiple-output (MIMO) detection is essential for practical systems. To reduce the computational complexity and high power consumption in MIMO detection process, we propose a memristor-based analog circuit for massive MIMO detection in this letter. First, we present the circuit architecture and operations for minimum mean squared error (MMSE) detection using a grid of synapse based on one memristor and two transistors (2T1M), and discuss its computational complexity and power consumption. Then, we extend the above circuit design to the MMSE successive interference cancellation (SIC) detection. Finally, the circuit is implemented using Simscape in MATLAB Simulink, and we show the superiority of the proposed memristor-based MIMO detection method in communication performance and power consumption. |
| doi_str_mv | 10.1109/LCOMM.2023.3322456 |
| format | Article |
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To reduce the computational complexity and high power consumption in MIMO detection process, we propose a memristor-based analog circuit for massive MIMO detection in this letter. First, we present the circuit architecture and operations for minimum mean squared error (MMSE) detection using a grid of synapse based on one memristor and two transistors (2T1M), and discuss its computational complexity and power consumption. Then, we extend the above circuit design to the MMSE successive interference cancellation (SIC) detection. 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To reduce the computational complexity and high power consumption in MIMO detection process, we propose a memristor-based analog circuit for massive MIMO detection in this letter. First, we present the circuit architecture and operations for minimum mean squared error (MMSE) detection using a grid of synapse based on one memristor and two transistors (2T1M), and discuss its computational complexity and power consumption. Then, we extend the above circuit design to the MMSE successive interference cancellation (SIC) detection. Finally, the circuit is implemented using Simscape in MATLAB Simulink, and we show the superiority of the proposed memristor-based MIMO detection method in communication performance and power consumption.</description><subject>Analog circuits</subject><subject>Circuit design</subject><subject>Complexity</subject><subject>Computational complexity</subject><subject>Error detection</subject><subject>Hardware</subject><subject>Low complexity</subject><subject>low power consumption</subject><subject>Massive MIMO</subject><subject>memristor</subject><subject>Memristors</subject><subject>MMSE</subject><subject>MMSE-SIC</subject><subject>Power consumption</subject><subject>Power demand</subject><subject>Synapses</subject><subject>Transistors</subject><issn>1089-7798</issn><issn>1558-2558</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkMFOwzAQRC0EEqXwA4hDJM4p63Uc29yqUqBSo0oIzlaSbqgLTYqdIvH3uLQHLrt7mNkZPcauOYw4B3M3nyyKYoSAYiQEYibzEzbgUuoU4ziNN2iTKmX0ObsIYQ0AGiUfMPVC_cq1H659T4oyBPdNSTErFskD9VT3rmvvk3FS0Ma70Hc-GW-3vivr1SU7a8rPQFfHPWRvj9PXyXM6XzzNJuN5WmOm-rSqS8EzJbWQTQ5mWVWYU1YqiaAqTVIuua6WDeWKFGSZbiSgaTQnwtgvN2LIbg9_Y-zXjkJv193OtzHSogHOTYYaogoPqtp3IXhq7Na7Tel_LAe7B2T_ANk9IHsEFE03B5Mjon8GVEIYFL-C4F-l</recordid><startdate>20231201</startdate><enddate>20231201</enddate><creator>Fang, Yiming</creator><creator>Chen, Li</creator><creator>You, Changsheng</creator><creator>Yin, Huarui</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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To reduce the computational complexity and high power consumption in MIMO detection process, we propose a memristor-based analog circuit for massive MIMO detection in this letter. First, we present the circuit architecture and operations for minimum mean squared error (MMSE) detection using a grid of synapse based on one memristor and two transistors (2T1M), and discuss its computational complexity and power consumption. Then, we extend the above circuit design to the MMSE successive interference cancellation (SIC) detection. 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| source | IEEE Electronic Library (IEL) |
| subjects | Analog circuits Circuit design Complexity Computational complexity Error detection Hardware Low complexity low power consumption Massive MIMO memristor Memristors MMSE MMSE-SIC Power consumption Power demand Synapses Transistors |
| title | Rethinking Massive MIMO Detection: A Memristor Approach |
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