A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology

In this work, the challenge of the I/O development roadmap is discussed. Utilizing design and technology co-optimization (DTCO), a cost-effective circuit solution of a 1.8-V general-purpose I/O (GPIO) is proposed in this work. It is not only designed to have comparable performance with standard I/O...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2025-02, Vol.60 (2), p.1-11
Hauptverfasser:	Chen, Wen-Chieh, Chen, Shih-Hung, Huang, Man-Ching, Chang, Shu-Wei, Hellings, Geert, Groeseneken, Guido
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit reliability Design Design and technology co-optimization (DTCO) design for reliability (DfR) Design optimization dynamic gate bias (DGB) Field effect transistors High-voltage techniques I/O buffer Input output analysis Integrated circuit reliability level shifter Logic gates mixed-voltage tolerant oxide reliability Reliability reliability array Reliability engineering Transient analysis Transistors
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