A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

Advanced artificial intelligence edge devices are expected to support floating-point (FP) multiply and accumulation operations while ensuring high energy efficiency and high inference accuracy. This work presents an FP compute-in-memory (CIM) macro that exploits the advantages of computing in the ti...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2024-01, Vol.59 (1), p.196-207
Hauptverfasser:	Wu, Ping-Chun, Su, Jian-Wei, Hong, Li-Yang, Ren, Jin-Sheng, Chien, Chih-Han, Chen, Ho-Yu, Ke, Chao-En, Hsiao, Hsu-Ming, Li, Sih-Han, Sheu, Shyh-Shyuan, Lo, Wei-Chung, Chang, Shih-Chieh, Lo, Chung-Chuan, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Chang, Meng-Fan
Format:	Artikel
Sprache:	eng
Schlagworte:	Accumulation Accuracy Artificial intelligence Artificial intelligence (AI) Computational efficiency compute-in-memory (CIM) Energy efficiency Floating point arithmetic floating-point (FP) In-memory computing inference Inference mechanisms Macrostructure Memory management Random access memory SRAM chips Static random access memory static random access memory (SRAM) Time-domain analysis
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