A Fractional- N PLL With Space-Time Averaging for Quantization Noise Reduction

This article presents a space-time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional-N phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in paralle...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2020-03, Vol.55 (3), p.602-614
Hauptverfasser:	Zhang, Yanlong, Sanyal, Arindam, Yu, Xueyi, Quan, Xing, Wen, Kailin, Tang, Xiyuan, Jin, Gang, Geng, Li, Sun, Nan
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Clocks data-weighted averaging (DWA) dynamic element matching (DEM) fractional-<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">N PLL Frequency conversion frequency synthesizer Phase locked loops Phase noise phase-locked loop (PLL) Quantization (signal) quantization noise reduction Voltage-controlled oscillators ΔΣ modulator (DSM)
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container_end_page	614
container_issue	3
container_start_page	602
container_title	IEEE journal of solid-state circuits
container_volume	55
creator	Zhang, Yanlong Sanyal, Arindam Yu, Xueyi Quan, Xing Wen, Kailin Tang, Xiyuan Jin, Gang Geng, Li Sun, Nan
description	This article presents a space-time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional-N phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional ΔΣ modulator (DSM) and a dynamic element matching (DEM) block. To reduce the divider power, this article also proposes a way to achieve spatial averaging using only one divider and phase selection. A prototype 2.4-GHz fractional-N PLL is implemented in a 40-nm CMOS process. Measurement results show that the proposed technique reduces the phase noise by 10 and 21 dB at the 1and 10-MHz offset, respectively, leading to a reduction of the integrated rms jitter from 9.55 to 2.26 ps.
doi_str_mv	10.1109/JSSC.2019.2950154
format	Article
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Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional ΔΣ modulator (DSM) and a dynamic element matching (DEM) block. To reduce the divider power, this article also proposes a way to achieve spatial averaging using only one divider and phase selection. A prototype 2.4-GHz fractional-N PLL is implemented in a 40-nm CMOS process. Measurement results show that the proposed technique reduces the phase noise by 10 and 21 dB at the 1and 10-MHz offset, respectively, leading to a reduction of the integrated rms jitter from 9.55 to 2.26 ps.</abstract><pub>IEEE</pub><doi>10.1109/JSSC.2019.2950154</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-5536-8385</orcidid><orcidid>https://orcid.org/0000-0003-4045-6291</orcidid><orcidid>https://orcid.org/0000-0003-2181-9042</orcidid><orcidid>https://orcid.org/0000-0003-4002-9281</orcidid><orcidid>https://orcid.org/0000-0002-6558-0718</orcidid><orcidid>https://orcid.org/0000-0002-8717-3160</orcidid><orcidid>https://orcid.org/0000-0002-3373-2561</orcidid></addata></record>
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subjects	Bandwidth Clocks data-weighted averaging (DWA) dynamic element matching (DEM) fractional-<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">N PLL Frequency conversion frequency synthesizer Phase locked loops Phase noise phase-locked loop (PLL) Quantization (signal) quantization noise reduction Voltage-controlled oscillators ΔΣ modulator (DSM)
title	A Fractional- N PLL With Space-Time Averaging for Quantization Noise Reduction
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