A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications
A dual-loop eight-channel electrocardiogram (ECG) recording system with the fast settling mode is proposed for wireless real-time 12-lead ECG applications. It employs the frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). The FDM technique allows using smaller input...
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Veröffentlicht in: | IEEE journal of solid-state circuits 2019-07, Vol.54 (7), p.1895-1906 |
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container_title | IEEE journal of solid-state circuits |
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creator | Zeng, Lei Liu, Boxiao Heng, Chun-Huat |
description | A dual-loop eight-channel electrocardiogram (ECG) recording system with the fast settling mode is proposed for wireless real-time 12-lead ECG applications. It employs the frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). The FDM technique allows using smaller input capacitor and sharing of programmable gain amplifier (PGA), buffer, and ADC to achieve smaller area. To suppress the dc offset of bio-signal with faster settling, dual dc servo loops are proposed. The main loop employs the least-mean-square (LMS) algorithm in the digital domain to extract the dc offsets in different frequency channels. An auxiliary fast settling loop (FSL) in the analog domain can be enabled to shorten the settling time from 14 s down to only 0.6 s. A 16-bit \Sigma \Delta ADC, including the decimation filter, is adopted to achieve high resolution and avoid using high Q anti-aliasing filter in the analog domain. The MCIA achieves 112.5-dB common mode rejection ratio (CMRR), 113.0-dB power supply rejection ratio (PSRR), and 1.44- \mu ~V_{\mathbf {rms}} noise performance. The MCIA occupies only 0.3 mm 2 and consumes 60 \mu \text{W} for eight channels. The whole ECG recording system was implemented in 130-nm CMOS technology. |
doi_str_mv | 10.1109/JSSC.2019.2903471 |
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It employs the frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). The FDM technique allows using smaller input capacitor and sharing of programmable gain amplifier (PGA), buffer, and ADC to achieve smaller area. To suppress the dc offset of bio-signal with faster settling, dual dc servo loops are proposed. The main loop employs the least-mean-square (LMS) algorithm in the digital domain to extract the dc offsets in different frequency channels. An auxiliary fast settling loop (FSL) in the analog domain can be enabled to shorten the settling time from 14 s down to only 0.6 s. A 16-bit <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> ADC, including the decimation filter, is adopted to achieve high resolution and avoid using high Q anti-aliasing filter in the analog domain. The MCIA achieves 112.5-dB common mode rejection ratio (CMRR), 113.0-dB power supply rejection ratio (PSRR), and 1.44-<inline-formula> <tex-math notation="LaTeX">\mu ~V_{\mathbf {rms}} </tex-math></inline-formula> noise performance. The MCIA occupies only 0.3 mm 2 and consumes 60 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> for eight channels. The whole ECG recording system was implemented in 130-nm CMOS technology.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2019.2903471</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Aliasing ; Amplification ; Capacitors ; Channels ; Choppers (circuits) ; Chopping ; CMOS ; electrocardiogram (ECG) readout ; Electrocardiography ; Electrodes ; Electronics packaging ; fast settling ; Frequency division multiplexing ; frequency division multiplexing (FDM) ; Gain ; multi-channel ; Noise levels ; Offsets ; Power supplies ; Recording ; Rejection ; Servomotors ; Settling ; wireless application</subject><ispartof>IEEE journal of solid-state circuits, 2019-07, Vol.54 (7), p.1895-1906</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-c1349f7a3599e4b25d9c783bdf36234407233bf31b3987a23562dfe420f71c03</citedby><cites>FETCH-LOGICAL-c293t-c1349f7a3599e4b25d9c783bdf36234407233bf31b3987a23562dfe420f71c03</cites><orcidid>0000-0002-8568-6616 ; 0000-0002-7117-6092 ; 0000-0002-5696-8403</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8674765$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,778,782,794,27911,27912,54745</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8674765$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zeng, Lei</creatorcontrib><creatorcontrib>Liu, Boxiao</creatorcontrib><creatorcontrib>Heng, Chun-Huat</creatorcontrib><title>A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[A dual-loop eight-channel electrocardiogram (ECG) recording system with the fast settling mode is proposed for wireless real-time 12-lead ECG applications. It employs the frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). The FDM technique allows using smaller input capacitor and sharing of programmable gain amplifier (PGA), buffer, and ADC to achieve smaller area. To suppress the dc offset of bio-signal with faster settling, dual dc servo loops are proposed. The main loop employs the least-mean-square (LMS) algorithm in the digital domain to extract the dc offsets in different frequency channels. An auxiliary fast settling loop (FSL) in the analog domain can be enabled to shorten the settling time from 14 s down to only 0.6 s. A 16-bit <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> ADC, including the decimation filter, is adopted to achieve high resolution and avoid using high Q anti-aliasing filter in the analog domain. The MCIA achieves 112.5-dB common mode rejection ratio (CMRR), 113.0-dB power supply rejection ratio (PSRR), and 1.44-<inline-formula> <tex-math notation="LaTeX">\mu ~V_{\mathbf {rms}} </tex-math></inline-formula> noise performance. The MCIA occupies only 0.3 mm 2 and consumes 60 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> for eight channels. The whole ECG recording system was implemented in 130-nm CMOS technology.]]></description><subject>Algorithms</subject><subject>Aliasing</subject><subject>Amplification</subject><subject>Capacitors</subject><subject>Channels</subject><subject>Choppers (circuits)</subject><subject>Chopping</subject><subject>CMOS</subject><subject>electrocardiogram (ECG) readout</subject><subject>Electrocardiography</subject><subject>Electrodes</subject><subject>Electronics packaging</subject><subject>fast settling</subject><subject>Frequency division multiplexing</subject><subject>frequency division multiplexing (FDM)</subject><subject>Gain</subject><subject>multi-channel</subject><subject>Noise levels</subject><subject>Offsets</subject><subject>Power supplies</subject><subject>Recording</subject><subject>Rejection</subject><subject>Servomotors</subject><subject>Settling</subject><subject>wireless application</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kF1LwzAUhoMoOKc_QLwJeJ2ZrzbN5ajbVCqCHehdSNtk6-iammQX-_euTLw6vJznPQceAO4JnhGC5dNbWeYziomcUYkZF-QCTEiSZIgI9n0JJhiTDEmK8TW4CWF3ipxnZALUHD4fdIcK5wa4aDfbiPKt7nvTwUW-gp-mdr5p-w0sjyGaPfxq4xYudYiwNDF24-bdNQZa5yGhqDC6gfNh6Npax9b14RZcWd0Fc_c3p2C9XKzzF1R8rF7zeYFqKllENWFcWqFZIqXhFU0aWYuMVY1lKWWcY0EZqywjFZOZ0JQlKW2s4RRbQWrMpuDxfHbw7udgQlQ7d_D96aOilGdpQhkdKXKmau9C8Maqwbd77Y-KYDVqVKNGNWpUfxpPnYdzpzXG_PNZKrhIE_YLRRhroA</recordid><startdate>20190701</startdate><enddate>20190701</enddate><creator>Zeng, Lei</creator><creator>Liu, Boxiao</creator><creator>Heng, Chun-Huat</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-8568-6616</orcidid><orcidid>https://orcid.org/0000-0002-7117-6092</orcidid><orcidid>https://orcid.org/0000-0002-5696-8403</orcidid></search><sort><creationdate>20190701</creationdate><title>A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications</title><author>Zeng, Lei ; Liu, Boxiao ; Heng, Chun-Huat</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-c1349f7a3599e4b25d9c783bdf36234407233bf31b3987a23562dfe420f71c03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Algorithms</topic><topic>Aliasing</topic><topic>Amplification</topic><topic>Capacitors</topic><topic>Channels</topic><topic>Choppers (circuits)</topic><topic>Chopping</topic><topic>CMOS</topic><topic>electrocardiogram (ECG) readout</topic><topic>Electrocardiography</topic><topic>Electrodes</topic><topic>Electronics packaging</topic><topic>fast settling</topic><topic>Frequency division multiplexing</topic><topic>frequency division multiplexing (FDM)</topic><topic>Gain</topic><topic>multi-channel</topic><topic>Noise levels</topic><topic>Offsets</topic><topic>Power supplies</topic><topic>Recording</topic><topic>Rejection</topic><topic>Servomotors</topic><topic>Settling</topic><topic>wireless application</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zeng, Lei</creatorcontrib><creatorcontrib>Liu, Boxiao</creatorcontrib><creatorcontrib>Heng, Chun-Huat</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zeng, Lei</au><au>Liu, Boxiao</au><au>Heng, Chun-Huat</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2019-07-01</date><risdate>2019</risdate><volume>54</volume><issue>7</issue><spage>1895</spage><epage>1906</epage><pages>1895-1906</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[A dual-loop eight-channel electrocardiogram (ECG) recording system with the fast settling mode is proposed for wireless real-time 12-lead ECG applications. It employs the frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). The FDM technique allows using smaller input capacitor and sharing of programmable gain amplifier (PGA), buffer, and ADC to achieve smaller area. To suppress the dc offset of bio-signal with faster settling, dual dc servo loops are proposed. The main loop employs the least-mean-square (LMS) algorithm in the digital domain to extract the dc offsets in different frequency channels. An auxiliary fast settling loop (FSL) in the analog domain can be enabled to shorten the settling time from 14 s down to only 0.6 s. A 16-bit <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> ADC, including the decimation filter, is adopted to achieve high resolution and avoid using high Q anti-aliasing filter in the analog domain. The MCIA achieves 112.5-dB common mode rejection ratio (CMRR), 113.0-dB power supply rejection ratio (PSRR), and 1.44-<inline-formula> <tex-math notation="LaTeX">\mu ~V_{\mathbf {rms}} </tex-math></inline-formula> noise performance. The MCIA occupies only 0.3 mm 2 and consumes 60 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> for eight channels. The whole ECG recording system was implemented in 130-nm CMOS technology.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2019.2903471</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0002-8568-6616</orcidid><orcidid>https://orcid.org/0000-0002-7117-6092</orcidid><orcidid>https://orcid.org/0000-0002-5696-8403</orcidid></addata></record> |
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subjects | Algorithms Aliasing Amplification Capacitors Channels Choppers (circuits) Chopping CMOS electrocardiogram (ECG) readout Electrocardiography Electrodes Electronics packaging fast settling Frequency division multiplexing frequency division multiplexing (FDM) Gain multi-channel Noise levels Offsets Power supplies Recording Rejection Servomotors Settling wireless application |
title | A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications |
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