A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operat...

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Veröffentlicht in:IEEE journal of solid-state circuits 2019-01, Vol.54 (1), p.43-54
Hauptverfasser: Poulton, John W., Wilson, John M., Turner, Walker J., Zimmer, Brian, Chen, Xi, Kudva, Sudhir S., Song, Sanquan, Tell, Stephen G., Nedovic, Nikola, Zhao, Wenxu, Sudhakaran, Sunil R., Gray, C. Thomas, Dally, William J.
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container_end_page 54
container_issue 1
container_start_page 43
container_title IEEE journal of solid-state circuits
container_volume 54
creator Poulton, John W.
Wilson, John M.
Turner, Walker J.
Zimmer, Brian
Chen, Xi
Kudva, Sudhir S.
Song, Sanquan
Tell, Stephen G.
Nedovic, Nikola
Zhao, Wenxu
Sudhakaran, Sunil R.
Gray, C. Thomas
Dally, William J.
description This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . Overall link die area is 686 \mu \text{m}\,\,\times 565 \mu \text{m} with the transceiver circuitry taking up 20% of the area. The transceiver's on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.
doi_str_mv 10.1109/JSSC.2018.2875092
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The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . 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Thomas</creatorcontrib><creatorcontrib>Dally, William J.</creatorcontrib><title>A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . 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Thomas</au><au>Dally, William J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2019-01</date><risdate>2019</risdate><volume>54</volume><issue>1</issue><spage>43</spage><epage>54</epage><pages>43-54</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . Overall link die area is 686 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}\,\,\times </tex-math></inline-formula> 565 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> with the transceiver circuitry taking up 20% of the area. The transceiver's on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2018.2875092</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0002-7368-4787</orcidid><orcidid>https://orcid.org/0000-0001-9230-7605</orcidid><orcidid>https://orcid.org/0000-0002-9239-9797</orcidid><orcidid>https://orcid.org/0000-0001-8488-3020</orcidid><orcidid>https://orcid.org/0000-0002-5137-5617</orcidid></addata></record>
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source IEEE Electronic Library (IEL)
subjects Attenuation
Bit error rate
Circuit boards
Circuits
Clock forwarding
Clocks
CMOS
Delays
dynamic voltage scaling
Energy efficiency
Frequency response
ground-referenced signaling (GRS)
Integrated circuit interconnections
multi-chip modules (MCM)
Phase locked loops
Power consumption
Power supplies
Printed circuits
Receivers
Regulators
single-ended (SE) signaling
Transmitters
Vibration
Voltage regulators
title A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
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