A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operat...
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Veröffentlicht in: | IEEE journal of solid-state circuits 2019-01, Vol.54 (1), p.43-54 |
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creator | Poulton, John W. Wilson, John M. Turner, Walker J. Zimmer, Brian Chen, Xi Kudva, Sudhir S. Song, Sanquan Tell, Stephen G. Nedovic, Nikola Zhao, Wenxu Sudhakaran, Sunil R. Gray, C. Thomas Dally, William J. |
description | This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . Overall link die area is 686 \mu \text{m}\,\,\times 565 \mu \text{m} with the transceiver circuitry taking up 20% of the area. The transceiver's on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply. |
doi_str_mv | 10.1109/JSSC.2018.2875092 |
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Thomas ; Dally, William J.</creator><creatorcontrib>Poulton, John W. ; Wilson, John M. ; Turner, Walker J. ; Zimmer, Brian ; Chen, Xi ; Kudva, Sudhir S. ; Song, Sanquan ; Tell, Stephen G. ; Nedovic, Nikola ; Zhao, Wenxu ; Sudhakaran, Sunil R. ; Gray, C. Thomas ; Dally, William J.</creatorcontrib><description><![CDATA[This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . Overall link die area is 686 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}\,\,\times </tex-math></inline-formula> 565 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> with the transceiver circuitry taking up 20% of the area. The transceiver's on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2018.2875092</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Attenuation ; Bit error rate ; Circuit boards ; Circuits ; Clock forwarding ; Clocks ; CMOS ; Delays ; dynamic voltage scaling ; Energy efficiency ; Frequency response ; ground-referenced signaling (GRS) ; Integrated circuit interconnections ; multi-chip modules (MCM) ; Phase locked loops ; Power consumption ; Power supplies ; Printed circuits ; Receivers ; Regulators ; single-ended (SE) signaling ; Transmitters ; Vibration ; Voltage regulators</subject><ispartof>IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.43-54</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-e80e52dc09b2c0758a76fe017816a849405f9fb1a4440ad47a7693fb0bf3db993</citedby><cites>FETCH-LOGICAL-c293t-e80e52dc09b2c0758a76fe017816a849405f9fb1a4440ad47a7693fb0bf3db993</cites><orcidid>0000-0002-7368-4787 ; 0000-0001-9230-7605 ; 0000-0002-9239-9797 ; 0000-0001-8488-3020 ; 0000-0002-5137-5617</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8528390$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8528390$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Poulton, John W.</creatorcontrib><creatorcontrib>Wilson, John M.</creatorcontrib><creatorcontrib>Turner, Walker J.</creatorcontrib><creatorcontrib>Zimmer, Brian</creatorcontrib><creatorcontrib>Chen, Xi</creatorcontrib><creatorcontrib>Kudva, Sudhir S.</creatorcontrib><creatorcontrib>Song, Sanquan</creatorcontrib><creatorcontrib>Tell, Stephen G.</creatorcontrib><creatorcontrib>Nedovic, Nikola</creatorcontrib><creatorcontrib>Zhao, Wenxu</creatorcontrib><creatorcontrib>Sudhakaran, Sunil R.</creatorcontrib><creatorcontrib>Gray, C. Thomas</creatorcontrib><creatorcontrib>Dally, William J.</creatorcontrib><title>A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . Overall link die area is 686 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}\,\,\times </tex-math></inline-formula> 565 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> with the transceiver circuitry taking up 20% of the area. The transceiver's on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.]]></description><subject>Attenuation</subject><subject>Bit error rate</subject><subject>Circuit boards</subject><subject>Circuits</subject><subject>Clock forwarding</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Delays</subject><subject>dynamic voltage scaling</subject><subject>Energy efficiency</subject><subject>Frequency response</subject><subject>ground-referenced signaling (GRS)</subject><subject>Integrated circuit interconnections</subject><subject>multi-chip modules (MCM)</subject><subject>Phase locked loops</subject><subject>Power consumption</subject><subject>Power supplies</subject><subject>Printed circuits</subject><subject>Receivers</subject><subject>Regulators</subject><subject>single-ended (SE) signaling</subject><subject>Transmitters</subject><subject>Vibration</subject><subject>Voltage regulators</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kcFq3DAQhkVpods0D1B6EfRa7Y5k2ZaOy5JuEhY2ZJPQm5Ht0aLEK7mSXcgD9T1js6Gn4We-b-bwE_KNw5Jz0Kvbw2GzFMDVUqgyBy0-kAXPc8V4mf3-SBYwrZgWAJ_Jl5Sepyil4gvyb035kpesv13VP6nI2bZepVXvPN3GMPqW3aPFiL7Blh6cP3bIrnw7B4zOdHTn_Au1IdK9tYwa39K9Z3emeTFHpJtwOo3eNWZwwdPHNPnU0LsYGkzpTD_gqcdohjEiW7emH9xfpE-hG2b_Ho9jZ4YQv5JP1nQJL9_nBXn8dfWwuWa7_fZms96xRuhsYKgAc9E2oGvRQJkrUxYWgZeKF0ZJLSG32tbcSCnBtLKc9jqzNdQ2a2utswvy43y3j-HPiGmonsMY_fSyErzQsgDIi4niZ6qJIaWItuqjO5n4WnGo5jaquY1qbqN6b2Nyvp8dh4j_eZULlWnI3gBQc4TY</recordid><startdate>201901</startdate><enddate>201901</enddate><creator>Poulton, John W.</creator><creator>Wilson, John M.</creator><creator>Turner, Walker J.</creator><creator>Zimmer, Brian</creator><creator>Chen, Xi</creator><creator>Kudva, Sudhir S.</creator><creator>Song, Sanquan</creator><creator>Tell, Stephen G.</creator><creator>Nedovic, Nikola</creator><creator>Zhao, Wenxu</creator><creator>Sudhakaran, Sunil R.</creator><creator>Gray, C. Thomas</creator><creator>Dally, William J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-7368-4787</orcidid><orcidid>https://orcid.org/0000-0001-9230-7605</orcidid><orcidid>https://orcid.org/0000-0002-9239-9797</orcidid><orcidid>https://orcid.org/0000-0001-8488-3020</orcidid><orcidid>https://orcid.org/0000-0002-5137-5617</orcidid></search><sort><creationdate>201901</creationdate><title>A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator</title><author>Poulton, John W. ; Wilson, John M. ; Turner, Walker J. ; Zimmer, Brian ; Chen, Xi ; Kudva, Sudhir S. ; Song, Sanquan ; Tell, Stephen G. ; Nedovic, Nikola ; Zhao, Wenxu ; Sudhakaran, Sunil R. ; Gray, C. Thomas ; Dally, William J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-e80e52dc09b2c0758a76fe017816a849405f9fb1a4440ad47a7693fb0bf3db993</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Attenuation</topic><topic>Bit error rate</topic><topic>Circuit boards</topic><topic>Circuits</topic><topic>Clock forwarding</topic><topic>Clocks</topic><topic>CMOS</topic><topic>Delays</topic><topic>dynamic voltage scaling</topic><topic>Energy efficiency</topic><topic>Frequency response</topic><topic>ground-referenced signaling (GRS)</topic><topic>Integrated circuit interconnections</topic><topic>multi-chip modules (MCM)</topic><topic>Phase locked loops</topic><topic>Power consumption</topic><topic>Power supplies</topic><topic>Printed circuits</topic><topic>Receivers</topic><topic>Regulators</topic><topic>single-ended (SE) signaling</topic><topic>Transmitters</topic><topic>Vibration</topic><topic>Voltage regulators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Poulton, John W.</creatorcontrib><creatorcontrib>Wilson, John M.</creatorcontrib><creatorcontrib>Turner, Walker J.</creatorcontrib><creatorcontrib>Zimmer, Brian</creatorcontrib><creatorcontrib>Chen, Xi</creatorcontrib><creatorcontrib>Kudva, Sudhir S.</creatorcontrib><creatorcontrib>Song, Sanquan</creatorcontrib><creatorcontrib>Tell, Stephen G.</creatorcontrib><creatorcontrib>Nedovic, Nikola</creatorcontrib><creatorcontrib>Zhao, Wenxu</creatorcontrib><creatorcontrib>Sudhakaran, Sunil R.</creatorcontrib><creatorcontrib>Gray, C. Thomas</creatorcontrib><creatorcontrib>Dally, William J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Poulton, John W.</au><au>Wilson, John M.</au><au>Turner, Walker J.</au><au>Zimmer, Brian</au><au>Chen, Xi</au><au>Kudva, Sudhir S.</au><au>Song, Sanquan</au><au>Tell, Stephen G.</au><au>Nedovic, Nikola</au><au>Zhao, Wenxu</au><au>Sudhakaran, Sunil R.</au><au>Gray, C. Thomas</au><au>Dally, William J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2019-01</date><risdate>2019</risdate><volume>54</volume><issue>1</issue><spage>43</spage><epage>54</epage><pages>43-54</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10 −15 . A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10 −15 . Overall link die area is 686 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}\,\,\times </tex-math></inline-formula> 565 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> with the transceiver circuitry taking up 20% of the area. The transceiver's on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2018.2875092</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0002-7368-4787</orcidid><orcidid>https://orcid.org/0000-0001-9230-7605</orcidid><orcidid>https://orcid.org/0000-0002-9239-9797</orcidid><orcidid>https://orcid.org/0000-0001-8488-3020</orcidid><orcidid>https://orcid.org/0000-0002-5137-5617</orcidid></addata></record> |
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subjects | Attenuation Bit error rate Circuit boards Circuits Clock forwarding Clocks CMOS Delays dynamic voltage scaling Energy efficiency Frequency response ground-referenced signaling (GRS) Integrated circuit interconnections multi-chip modules (MCM) Phase locked loops Power consumption Power supplies Printed circuits Receivers Regulators single-ended (SE) signaling Transmitters Vibration Voltage regulators |
title | A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator |
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